Patents by Inventor Pulkit Khandelwal
Pulkit Khandelwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949629Abstract: A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.Type: GrantFiled: April 19, 2022Date of Patent: April 2, 2024Assignee: Astera Labs, Inc.Inventors: Enrique Musoll, Subbarao Arumilli, Ken (Keqin) Han, Pulkit Khandelwal, Casey Morrison
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Patent number: 11941436Abstract: An integrated-circuit retimer selectively logs information corresponding to mission-mode data, received and transmitted via counterpart high-bandwidth data interfaces, in real-time and accordance with contents of a logging control storage written by an external component during retimer run time.Type: GrantFiled: April 26, 2021Date of Patent: March 26, 2024Assignee: Astera Labs, Inc.Inventors: Ken (Keqin) Han, Casey Morrison, Charan Enugala, Pulkit Khandelwal, Vikas Khandelwal
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Patent number: 11853115Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: September 27, 2022Date of Patent: December 26, 2023Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Patent number: 11487317Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: September 20, 2021Date of Patent: November 1, 2022Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Patent number: 11424905Abstract: First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.Type: GrantFiled: April 10, 2021Date of Patent: August 23, 2022Assignee: Astera Labs, Inc.Inventors: Enrique Musoll, Casey Morrison, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli
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Patent number: 11349626Abstract: A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.Type: GrantFiled: July 8, 2020Date of Patent: May 31, 2022Assignee: Astera Labs, Inc.Inventors: Enrique Musoll, Subbarao Arumilli, Ken (Keqin) Han, Pulkit Khandelwal, Casey Morrison
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Patent number: 11327913Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.Type: GrantFiled: September 21, 2020Date of Patent: May 10, 2022Assignee: Astera Labs, Inc.Inventors: Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Vivek Trivedi
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Patent number: 11258696Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.Type: GrantFiled: June 4, 2020Date of Patent: February 22, 2022Assignee: Asiera Labs, Inc.Inventors: Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Ken (Keqin) Han, Charan Enugala, Vivek Trivedi, Chi Feng
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Patent number: 11150687Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: July 10, 2020Date of Patent: October 19, 2021Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Patent number: 10128955Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.Type: GrantFiled: May 25, 2018Date of Patent: November 13, 2018Assignee: INPHI CORPORATIONInventors: Todd Rope, Radhakrishnan L. Nagarajan, Jamal Riani, Pulkit Khandelwal
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Publication number: 20180294884Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.Type: ApplicationFiled: May 25, 2018Publication date: October 11, 2018Inventors: Todd ROPE, Radhakrishnan L. NAGARAJAN, Jamal RIANI, Pulkit KHANDELWAL
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Patent number: 10009109Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.Type: GrantFiled: August 28, 2017Date of Patent: June 26, 2018Assignee: INPHI CORPORATIONInventors: Todd Rope, Radhakrishnan L. Nagarajan, Jamal Riani, Pulkit Khandelwal
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Publication number: 20170373759Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.Type: ApplicationFiled: August 28, 2017Publication date: December 28, 2017Inventors: Todd ROPE, Radhakrishnan L. NAGARAJAN, Jamal RIANI, Pulkit KHANDELWAL
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Patent number: 9825756Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: GrantFiled: December 9, 2016Date of Patent: November 21, 2017Assignee: INPHI CORPORATIONInventors: Halil Cirit, Karthik Gopalakrishnan, Pulkit Khandelwal, Ravindran Mohanavelu
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Patent number: 9780881Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.Type: GrantFiled: October 13, 2015Date of Patent: October 3, 2017Assignee: INPHI CORPORATIONInventors: Todd Rope, Radhakrishnan L. Nagarajan, Jamal Riani, Pulkit Khandelwal
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Publication number: 20170207908Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: ApplicationFiled: December 9, 2016Publication date: July 20, 2017Inventors: Halil CIRIT, Karthik GOPALAKRISHNAN, Pulkit KHANDELWAL, Ravindran MOHANAVELU
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Patent number: 9548858Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: GrantFiled: January 18, 2016Date of Patent: January 17, 2017Assignee: INPHI CORPORATIONInventors: Halil Cirit, Karthik Gopalakrishnan, Pulkit Khandelwal, Ravindran Mohanavelu