Patents by Inventor Pulugurtha Markondeya Raj
Pulugurtha Markondeya Raj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9173282Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.Type: GrantFiled: March 31, 2011Date of Patent: October 27, 2015Assignee: Georgia Tech Research CorporationInventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venkatesh Sundaram, Rao R. Tummala
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Patent number: 8970036Abstract: Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.Type: GrantFiled: September 20, 2011Date of Patent: March 3, 2015Assignee: Georgia Tech Research CorporationInventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venkatesh V. Sundaram, Rao R. Tummala, Xian Qin
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Publication number: 20130270695Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.Type: ApplicationFiled: September 20, 2011Publication date: October 17, 2013Applicant: Georgia Tech Research CorporationInventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venky Sundaraman, Rao R. Tummala, Xian Qin
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Publication number: 20130107485Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.Type: ApplicationFiled: March 31, 2011Publication date: May 2, 2013Applicant: Georgia Tech Research CorporationInventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venkatesh Sundaram, Rao R. Tummala
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Patent number: 7557448Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.Type: GrantFiled: August 27, 2007Date of Patent: July 7, 2009Assignee: Georgia Tech Research CorporationInventors: Ankur Aggarwal, Pulugurtha Markondeya Raj, Rao R. Tummala
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Patent number: 7556189Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.Type: GrantFiled: May 26, 2005Date of Patent: July 7, 2009Assignee: Georgia Tech Research CorporationInventors: Ankur Aggarwal, Isaac Robin Abothu, Pulugurtha Markondeya Raj, Rao R. Tummala
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Publication number: 20080136035Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.Type: ApplicationFiled: August 27, 2007Publication date: June 12, 2008Applicant: Georgia Tech Research CorporationInventors: Ankur Aggarwal, Pulugurtha Markondeya Raj, Rao R. Tummala
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Patent number: 7262075Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.Type: GrantFiled: January 10, 2005Date of Patent: August 28, 2007Assignee: Georgia Tech Research Corp.Inventors: Ankur Aggarwal, Pulugurtha Markondeya Raj, Rao R. Tummala