Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

Abstract: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

Abstract: An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition. The control algorithm also includes a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port, executing a memory write and setting values to the ports on the NVM module to assert the complement of the program condition.

Abstract: An electronic component heat dissipation apparatus and methods having a heat dissipation housing. The heat dissipation housing having an external wall and an internal wall defining outer chamber therebetween. The internal wall defines an internal chamber having an airflow inlet opening and an airflow outlet opening. The housing is aligned with at least one electronic component so as to define a thermal chimney through the internal chamber for the flow of heated air. The external wall has at least one external air opening configured to allow external air into the outer chamber. The internal wall has a plurality of heat dissipation nozzles. Each heat dissipation nozzle has an external air inlet opening located within the internal wall and an external air outlet opening located within the internal chamber. The diameter of the external air inlet opening is greater than the diameter of the external air outlet opening.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing collected web content are presented. A collection of web content may be maintained, wherein the collection of web content is divided into a plurality of sections, each of the plurality of sections comprising a subset of web content from a different webpage. An indication to export the collection of web content to a productivity application may be received. A plurality of attributes that each of the plurality of sections have a value for may be identified. A productivity application document may be populated with the plurality of attributes and the corresponding values from each of the sections.

Abstract: Methods and systems for thermal management of a telecommunications network having at least one wireless radio equipment system in communication with a plurality of radio heads. The wireless radio equipment system has a thermal management component. Each of the plurality of radio heads has a high operating temperature threshold. The methods and system configured to monitor the operating temperature of the plurality of radio heads by the thermal management component. If a determination by the thermal management component that at least one of the radio heads exceeds its high operating temperature threshold, a reconfiguring of the telecommunications network to reduce the operating temperature of the at least one of the plurality of radio heads.

Abstract: An electronic component heat dissipation apparatus and methods having a heat dissipation housing. The heat dissipation housing having an external wall and an internal wall defining outer chamber therebetween. The internal wall defines an internal chamber having an airflow inlet opening and an airflow outlet opening. The housing is aligned with at least one electronic component so as to define a thermal chimney through the internal chamber for the flow of heated air. The external wall has at least one external air opening configured to allow external air into the outer chamber. The internal wall has a plurality of heat dissipation nozzles. Each heat dissipation nozzle has an external air inlet opening located within the internal wall and an external air outlet opening located within the internal chamber. The diameter of the external air inlet opening is greater than the diameter of the external air outlet opening.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing collected web content are presented. A collection of web content may be maintained, wherein the collection of web content is divided into a plurality of sections, each of the plurality of sections comprising a subset of web content from a different webpage. An indication to export the collection of web content to a productivity application may be received. A plurality of attributes that each of the plurality of sections have a value for may be identified. A productivity application document may be populated with the plurality of attributes and the corresponding values from each of the sections.

Abstract: Methods, apparatuses, or computer program products are disclosed providing for the programmatic translation and ingestion of exported event data objects between an extrinsic event scheduling service and a collaborative documentation service via an extrinsic event consolidation system. The extrinsic event consolidation system provides for the generation of collaborative event documentation data structures based on exported event data objects comprising elements of an extrinsic event. The collaborative event documentation data structure may be used to generate exported event data objects to communicate elements of an extrinsic event to an extrinsic event scheduling service. Various processes are described for the translation of extrinsic event data objects between disparate services including multiple disparate extrinsic event scheduling services and disparate collaborative documentation services.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing collected web content are presented. A collection of web content may be maintained, wherein the collection of web content is divided into a plurality of sections, each of the plurality of sections comprising a subset of web content from a different webpage. An indication to export the collection of web content to a productivity application may be received. A plurality of attributes that each of the plurality of sections have a value for may be identified. A productivity application document may be populated with the plurality of attributes and the corresponding values from each of the sections.

Abstract: Methods, apparatus, and processor-readable storage media for transaction visibility framework implemented using artificial intelligence are provided herein.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing collected web content are presented. A collection of web content may be maintained, wherein the collection of web content is divided into a plurality of sections, each of the plurality of sections comprising a subset of web content from a different webpage. An indication to export the collection of web content to a productivity application may be received. A plurality of attributes that each of the plurality of sections have a value for may be identified. A productivity application document may be populated with the plurality of attributes and the corresponding values from each of the sections.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for collecting and surfacing web content are provided. First web content may be accessed and displayed in a web browser. An indication to add a subset of the first web content to a content collection pane integrated in the web browser may be received. The subset of the first web content may be displayed in the content collection pane of the web browser. Second web content from a second website may be accessed and displayed in the web browser. An indication to add a subset of the second web content to the content collection pane may be received. The subset of the first web content and the subset of the second web content may be displayed simultaneously in the content collection pane of the web browser.

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

Abstract: An exemplary fuse control arrangement can be provided, which can include, for example, a fuse control unit(s), which includes a test access method interface(s) and a programmable memory(ies), wherein the fuse control unit(s) is configured to provide fuse information to repair a memory(ies). The fuse control unit(s) can be coupled to the memory(ies) and the memory(ies) can be coupled to a register repair unit(s). The fuse control unit(s) can provide the register repair unit(s) with the fuse information to repair the memory(ies).

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

Abstract: Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).