Patents by Inventor Puneet Harischandra Suvarna

Puneet Harischandra Suvarna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784171
    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Publication number: 20200035569
    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 30, 2020
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10510622
    Abstract: A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10497798
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Patent number: 10446659
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Rohit Galatage, Puneet Harischandra Suvarna
  • Patent number: 10418449
    Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bipul C. Paul, Ruilong Xie, Puneet Harischandra Suvarna
  • Publication number: 20190252267
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Publication number: 20190214469
    Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Bipul C. Paul, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10347745
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Steven J. Bentley, Daniel Chanemougame
  • Patent number: 10332969
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 10312154
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Patent number: 10304833
    Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Bipul C. Paul, Ruilong Xie, Bartlomiej Jan Pawlak, Lars W. Liebmann, Daniel Chanemougame, Nicholas V. LiCausi, Andreas Knorr
  • Publication number: 20190115444
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven BENTLEY, Rohit GALATAGE, Puneet Harischandra Suvarna
  • Publication number: 20190115437
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 18, 2019
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20190088764
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: GLBOALFOUNDRIES INC.
    Inventors: Ruilong XIE, Steven BENTLEY, Puneet Harischandra SUVARNA, Chanro PARK, Min Gyu SUNG, Lars LIEBMANN, Su Chen FAN, Brent ANDERSON
  • Patent number: 10236379
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Patent number: 10170617
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES
    Inventors: Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Steven Bentley, Jody A. Fronheiser
  • Patent number: 10141414
    Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20180331213
    Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Applicant: GLOBAL FOUNDRIES INC.
    Inventors: Steven Bentley, Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak
  • Publication number: 20180226505
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Application
    Filed: February 3, 2017
    Publication date: August 9, 2018
    Inventors: Jiseok KIM, Hiroaki NIIMI, Hoon KIM, Puneet Harischandra SUVARNA, Steven BENTLEY, Jody A. FRONHEISER