Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

Abstract: Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure.

Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.

Abstract: Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

Abstract: Apparatus for sealing a puncture communicating with a blood vessel includes a bioabsorbable sealing member secured to one end of a filament or other retaining member. The sealing member is delivered through the puncture into the vessel, and retracted against the wall of the vessel to provide temporary hemostasis. The sealing member is rapidly absorbed after exposure within the vessel, e.g., to an aqueous or heated physiological environment (e.g., exposure to blood or body temperature), immediately or shortly after completing a medical procedure via the puncture, e.g., within the time period that the patient is ambulatory. Optionally, extravascular sealing material is delivered into the puncture proximal to the sealing member. The retaining member and/or extravascular material may be bioabsorbable, being absorbed at a slower rate than the sealing member. Alternatively, the filament is removed from the puncture after hemostasis is established.

Abstract: Apparatus for sealing a puncture communicating with a blood vessel includes a bioabsorbable sealing member secured to one end of a filament or other retaining member. The sealing member is delivered through the puncture into the vessel, and retracted against the wall of the vessel to provide temporary hemostasis. The sealing member is rapidly absorbed after exposure within the vessel, e.g., to an aqueous or heated physiological environment (e.g., exposure to blood or body temperature), immediately or shortly after completing a medical procedure via the puncture, e.g., within the time period that the patient is ambulatory optionally, extravascular sealing material is delivered into the puncture proximal to the sealing member. The retaining member and/or extravascular material may be bioabsorbable, being absorbed at a slower rate than the sealing member. Alternatively, the filament is removed from the puncture after hemostasis is established.