Patents by Inventor Puneet Singh

Puneet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120226701
    Abstract: A computer implemented method and system is provided for validating a user associated with one or more social networks. A validation platform associated with the social networks is provided. The validation platform identifies a user for the validation from the social networks. The validation platform retrieves social information of the identified user from the social networks. The social information comprises relationship information of and between the identified user and social contacts of the identified user on the social networks. The validation platform acquires feedback on the identified user from one or more of the social contacts. The validation platform generates one or more validation scores, for example, an evaluation score, a feedback authentication score, a user authentication score, a composite score, etc., for the identified user based on the retrieved social information and/or the acquired feedback.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Inventor: Puneet Singh
  • Publication number: 20120092767
    Abstract: A laminate article preferably including two or more layers adapted to be applied to a surface of a roadway that can function as a reflective marker, such as a lane marker or road feature marker. The article includes one or more reflective compounds, preferably particles, aggregates, or clusters that are partially embedded in an exposed outer surface layer of the article. In order to increase the durability of the material, protective media compounds are also present in the outer layer and extend outward therefrom with the protective material protruding a greater distance than the reflective compounds. The articles of the present invention are weather resistant, durable and resistant to damage by vehicles and snowplows.
    Type: Application
    Filed: September 11, 2009
    Publication date: April 19, 2012
    Inventors: Hemant A. Naik, Puneet Singh, Ratanjit Sondhe
  • Publication number: 20100070978
    Abstract: A method for managing storage for a desktop pool is described. The desktop pool includes a plurality of virtual machines (VMs), each VM having at least one virtual disk represented as a virtual disk image file on one of a plurality of datastores associated with the desktop pool. To identify a target datastore for a VM, a weight of each datastore is calculated. The weight may be a function of a virtual capacity of the datastore and the sum of maximum sizes of all the virtual disk image files on the datastore. The virtual capacity is a product of the data storage capacity of the datastore and an overcommit factor assigned to the datastore. The target datastore is selected as the datastore having the highest weight. The VM may is moved to or created on the target datastore.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 18, 2010
    Applicant: VMware, Inc.
    Inventors: Puneet Singh CHAWLA, Ke Jin, Frank Taylor, Keith Johnston, Amit Patel
  • Patent number: 7107552
    Abstract: A method and apparatus to analyze noise in a pulse logic digital circuit comprising identifying a channel connected component (CCC) in the pulse logic digital circuit design, said CCC comprising a pulse generator. Modifying the pulse logic digital circuit by disconnecting the pulse generator form an input of the CCC in the pulse logic digital circuit design. Turning on the pulse logic digital circuit, inputting a noise signal to the CCC and monitoring an output of the pulse logic digital circuit during the time the pulse logic digital circuit is turn on.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventor: Puneet Singh
  • Publication number: 20040255255
    Abstract: A method and apparatus to analyze noise in a pulse logic digital circuit comprising identifying a channel connected component (CCC) in the pulse logic digital circuit design, said CCC comprising a pulse generator. Modifying the pulse logic digital circuit by disconnecting the pulse generator form an input of the CCC in the pulse logic digital circuit design. Turning on the pulse logic digital circuit, inputting a noise signal to the CCC and monitoring an output of the pulse logic digital circuit during the time the pulse logic digital circuit is turn on.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Inventor: Puneet Singh
  • Patent number: 6748352
    Abstract: A scan cell design approach includes removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties. A formal verification assumption verification process is then performed on a schematic using assumptions generated from the reduced set of formal verification properties. An output of the assumption verification process indicates whether there is a potential contention site at logic coupled to the output of the scan cell.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: June 8, 2004
    Assignee: Intel Corporation
    Inventors: Joel T. Yuen, Kailasnath S. Maneparambil, Puneet Singh