Patents by Inventor Punit B. Shah

Punit B. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8145872
    Abstract: Database partition monitoring and dynamic logical partition reconfiguration in support of an autonomic self-tunable database management system are provided by an automated monitor that monitors one or more resource parameters in a logical partition running a database application in a logically partitioned data processing host. The monitor initiates dynamic logical partition reconfiguration in the event that the parameters vary from predetermined parameter values. In particular, the monitor can initiate removal of resources if one of the resource parameters is being underutilized and initiate addition of resources if one of the resource parameters is being overutilized. The monitor can also calculate an amount of resources to be removed or added. The monitor can interact directly with a dynamic logical partition reconfiguration function of the data processing host or it can utilize an intelligent intermediary that listens for a partition reconfiguration suggestion from the monitor.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Punit B. Shah, Nuzio Ruffolo, Enzo Cialini
  • Patent number: 8141061
    Abstract: A compiler utility assigns memory locations to alias-free variables within a computer program. The compiler utility allocates memory keys for the alias-free variables, such that access to the memory locations of the alias-free variables is granted to blocks of code that have knowledge of the memory keys. In response to a command by the user, the compiler generates code to detect violations of alias assumptions during execution of the computer program. During the compiling process, the compiler adds the generated code for detecting violations of alias assumptions to the compiled computer program.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Francis M. Bartucca, Billy R. Robinson, Punit B. Shah, Carlos P. Sosa
  • Publication number: 20100011381
    Abstract: A manage-analyze-plan-execute (MAPE) loop is performed on a system-wide basis in relation to subsystems of a computing system based on one or more parameters. Performing the MAPE loop results in a performance level at which each subsystem is to operate to conserve energy utilization on the system-wide basis such that the computing system still satisfies the parameters. The subsystem the performance level at which each subsystem is to operate is communicated to the subsystem. Each subsystem operates at the performance level communicated to the subsystem.
    Type: Application
    Filed: July 13, 2008
    Publication date: January 14, 2010
    Inventors: Punit B. Shah, Billy R. Robinson, Francis M. Bartucca, Carlos P. Sosa
  • Publication number: 20080115118
    Abstract: A method of detecting incorrect alias assumptions. A compiler utility assigns memory locations to alias-free variables, which a user asserts do not have aliases, within a computer program. The compiler utility allocates memory keys for the alias-free variables, such that access to the memory locations of the alias-free variables is granted to blocks of code that have knowledge of the memory keys. In response to a command by the user, the compiler generates code to detect violations of alias assumptions during execution of the computer program. During the compiling process, the compiler adds the generated code for detecting violations of alias assumptions to the compiled program code.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 15, 2008
    Inventors: Francis M. Bartucca, Billy R. Robinson, Punit B. Shah, Carlos P. Sosa
  • Publication number: 20080077868
    Abstract: A method, system, and computer-usable medium for visually representing resource usage in a multi-node data processing system. According to a preferred embodiment of the present invention a graphical user interface (GUI) stored in system memory visually expresses the multi-node data processing system as a collection of cubes, where each cube among the collection of cubes represents at least one node within the multi-node data processing system. The GUI specifies a currently-running application to measure a level of resources utilized by the currently-running application. The GUI indicates a type of resource information to be displayed and display the indicated type of resource information related to the currently-running application utilizing the collection of cubes.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 27, 2008
    Inventors: Francis M. Bartucca, Billy R. Robinson, Punit B. Shah, Carlos P. Sosa