Patents by Inventor Punit Kishore
Punit Kishore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11237587Abstract: Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.Type: GrantFiled: December 14, 2020Date of Patent: February 1, 2022Assignee: QUALCOMM INCORPORATEDInventors: Punit Kishore, Ankit Goyal, Srinivas Patil
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Patent number: 10996267Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.Type: GrantFiled: January 23, 2019Date of Patent: May 4, 2021Assignee: QUALCOMM INCORPORATEDInventors: Jais Abraham, Punit Kishore
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Patent number: 10877088Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.Type: GrantFiled: January 30, 2019Date of Patent: December 29, 2020Assignee: QUALCOMM IncorporatedInventors: Punit Kishore, Tomer Rafael Ben-Chen, Sharon Graif
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Publication number: 20200241070Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.Type: ApplicationFiled: January 30, 2019Publication date: July 30, 2020Inventors: Punit KISHORE, Tomer Rafael BEN-CHEN, Sharon GRAIF
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Publication number: 20200233031Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Jais ABRAHAM, Punit KISHORE
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Patent number: 10656203Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.Type: GrantFiled: February 18, 2019Date of Patent: May 19, 2020Assignee: QUALCOMM IncorporatedInventors: Punit Kishore, Jais Abraham, Pawan Chhabra
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Patent number: 10241148Abstract: One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.Type: GrantFiled: August 11, 2015Date of Patent: March 26, 2019Assignee: NVIDIA CORPORATIONInventors: Ashfaq Shaikh, Wen-Hung Lo, Punit Kishore, Amit Sanghani, Krishna Rajan
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Publication number: 20170045575Abstract: One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventors: Ashfaq SHAIKH, Wen-Hung LO, Punit KISHORE, Amit SANGHANI, Krishna RAJAN
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Patent number: 8943457Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.Type: GrantFiled: November 24, 2008Date of Patent: January 27, 2015Assignee: NVIDIA CorporationInventors: Amit Dinesh Sanghani, Punit Kishore
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Patent number: 8726205Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit at a first level higher than a second level at which design verification and/or design simulation of the electronic circuit is to be conducted, and representing instances of elements of the electronic circuit in a data structure. The method also includes parsing, at the first level, the design to automatically generate a list of regular expressions related to text-matching strings with the elements of the electronic circuit based on removing undesired instances related to the elements from the data structure, and pruning, at the second level, connectivity descriptors of the electronic circuit based on the automatically generated list of regular expressions. Further, the method includes optimizing the design verification and/or the design simulation at the second level based on the pruned connectivity descriptors thereof.Type: GrantFiled: April 15, 2013Date of Patent: May 13, 2014Assignee: Nvidia CorporationInventors: Amanulla Khan, Punit Kishore
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Publication number: 20100131910Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.Type: ApplicationFiled: November 24, 2008Publication date: May 27, 2010Applicant: NVIDIA CorporationInventors: Amit Dinesh Sanghani, Punit Kishore