Patents by Inventor Punit Minocha
Punit Minocha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7480686Abstract: A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.Type: GrantFiled: May 14, 2004Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Srinivas Chennupaty
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Patent number: 7461109Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.Type: GrantFiled: June 6, 2007Date of Patent: December 2, 2008Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Patent number: 7451169Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: June 15, 2006Date of Patent: November 11, 2008Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Publication number: 20070239810Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.Type: ApplicationFiled: June 6, 2007Publication date: October 11, 2007Inventors: DERRICK LIN, Punit Minocha, Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry Mennemeier, Benny Eitan
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Publication number: 20060235914Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: ApplicationFiled: June 15, 2006Publication date: October 19, 2006Inventors: Derrick Lin, Punit Minocha, Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry Mennemeier, Benny Eitan
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Patent number: 7117232Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: May 27, 2005Date of Patent: October 3, 2006Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Publication number: 20050219897Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: ApplicationFiled: May 27, 2005Publication date: October 6, 2005Inventors: Derrick Lin, Punit Minocha, Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry Mennemeier, Benny Eitan
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Patent number: 6901420Abstract: A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: July 18, 2003Date of Patent: May 31, 2005Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Publication number: 20040215681Abstract: A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.Type: ApplicationFiled: May 14, 2004Publication date: October 28, 2004Inventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Srinivas Chennupaty
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Patent number: 6738793Abstract: An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: February 14, 2001Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Srinivas Chennupaty
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Publication number: 20040024800Abstract: A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: ApplicationFiled: July 18, 2003Publication date: February 5, 2004Inventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Patent number: 6631389Abstract: An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: December 22, 2000Date of Patent: October 7, 2003Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Publication number: 20030023646Abstract: An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: ApplicationFiled: January 14, 2001Publication date: January 30, 2003Inventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Srinivas Chennupaty
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Publication number: 20010016861Abstract: An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: ApplicationFiled: December 22, 2000Publication date: August 23, 2001Inventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Patent number: 6275834Abstract: An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.Type: GrantFiled: March 4, 1996Date of Patent: August 14, 2001Assignee: Intel CorporationInventors: Derrick Chu Lin, Punit Minocha, Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan