Patents by Inventor Punit S. Kalra

Punit S. Kalra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reconfiguration of a programmable logic device using internal control
    Patent number: 7227378
    Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 5, 2007
    Assignee: Xilinx, Inc.
    Inventors: Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller, Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck
  • Reconfiguration of a programmable logic device using internal control
    Patent number: 6920627
    Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: July 19, 2005
    Assignee: XILINX, Inc.
    Inventors: Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller, Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck
  • Partial reconfiguration of a programmable logic device using an on-chip processor
    Patent number: 6907595
    Abstract: A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: June 14, 2005
    Assignee: Xilinx, Inc.
    Inventors: Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck, Stephen W. Trynosky, Jeffrey V. Lindholm, Trevor J. Bauer
  • Reconfiguration of a programmable logic device using internal control
    Publication number: 20040117755
    Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
    Type: Application
    Filed: February 28, 2003
    Publication date: June 17, 2004
    Applicant: Xilinx, Inc.
    Inventors: Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller, Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck
  • Partial reconfiguration of a programmable logic device using an on-chip processor
    Publication number: 20040113655
    Abstract: A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 17, 2004
    Applicant: Xilinx, Inc.
    Inventors: Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck, Stephen W. Trynosky, Jeffrey V. Lindholm, Trevor J. Bauer