Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.

Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

Abstract: The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes.

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.

Abstract: A HVMOS transistor structure includes a semiconductor substrate; a gate overlying the semiconductor substrate; a gate dielectric layer between the gate and the semiconductor substrate; a sidewall spacer on each sidewall of the gate; a drain structure in the semiconductor substrate on one side of the gate; an ion well of the first conductivity type in the semiconductor substrate; a source structure in the semiconductor substrate being space apart from the drain structure; and a channel region between the drain structure and the source structure, wherein the channel region substantially consisting of two gate-overlapping regions of the first conductivity type having doping concentrations different from each other.

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device with isolated drain. The method performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate, exposing portions of the semiconductor substrate; performing a first ion implant process on the portions of the semiconductor substrate exposed by the first patterned mask layer; performing a second ion implant process to a second well region exposed, forming a fourth well region between the first well region and the second well region; performing a third implant process to the second well region, forming a fifth well region overlying the fourth well region; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device with isolated drain. The method performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate, exposing portions of the semiconductor substrate; performing a first ion implant process on the portions of the semiconductor substrate exposed by the first patterned mask layer; performing a second ion implant process to a second well region exposed, forming a fourth well region between the first well region and the second well region; performing a third implant process to the second well region, forming a fifth well region overlying the fourth well region; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

Abstract: The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes.

Abstract: A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

Abstract: A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.