Patents by Inventor Purab Ranjan Sutradhar

Purab Ranjan Sutradhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Look-up table containing processor-in-memory cluster for data-intensive applications
    Patent number: 11775312
    Abstract: A processing element includes a PIM cluster configured to read data from and write data to an adjacent DRAM subarray, wherein the PIM cluster has a plurality of processing cores, each processing core of the plurality of processing cores containing a look-up table, and a router connected to each processing core, wherein the router is configured to communicate data among each processing core; and a controller unit configured to communicate with the router, wherein the controller unit contains an executable program of operational decomposition algorithms. The look-up tables can be programmable. A DRAM chip including a plurality of DRAM banks, each DRAM bank having a plurality of interleaved DRAM subarrays and a plurality of the PIM clusters configured to read data from and write data to an adjacent DRAM subarray is disclosed.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Rochester Institute of Technology
    Inventors: Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao, Mark Connolly, Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Allen Indovina
  • LOOK-UP TABLE CONTAINING PROCESSOR-IN-MEMORY CLUSTER FOR DATA-INTENSIVE APPLICATIONS
    Publication number: 20220326958
    Abstract: A processing element includes a PIM cluster configured to read data from and write data to an adjacent DRAM subarray, wherein the PIM cluster has a plurality of processing cores, each processing core of the plurality of processing cores containing a look-up table, and a router connected to each processing core, wherein the router is configured to communicate data among each processing core; and a controller unit configured to communicate with the router, wherein the controller unit contains an executable program of operational decomposition algorithms. The look-up tables can be programmable. A DRAM chip including a plurality of DRAM banks, each DRAM bank having a plurality of interleaved DRAM subarrays and a plurality of the PIM clusters configured to read data from and write data to an adjacent DRAM subarray is disclosed.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 13, 2022
    Applicant: Rochester Institute of Technology
    Inventors: Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao, Mark Connolly, Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Allen Indovina