Patents by Inventor Purna C. Nayak

Purna C. Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power clock gate circuit
    Patent number: 10996709
    Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
  • LOW POWER CLOCK GATE CIRCUIT
    Publication number: 20210064076
    Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu