Abstract: A system configured to minimize validation time associated with an integrated circuit design is provided. The system includes a client and a server. The client is configured to identify a test case for simulation with the integrated circuit design. The client is further configured to generate a verified file from the test case. The server is in communication with the client. The server is configured to maintain an initialized state. The server, when in the initialized state, is configured to receive the verified file from the client for execution, wherein after execution of the verified file, the server is enabled to communicate results to the client and the server resets to the initialized state. A method for submitting a test case for simulation of an integrated circuit design and a computer readable medium are also provided.

Abstract: A method and apparatus for generating identification numbers for PCI Express that provides unique generation and substantially increased system performance. A system having a PCI Express fabric and PCI devices connected thereto generates unique TAG identification numbers for transactions with substantially increased performance. The system generates and prepares up to three available TAG IDs in advance, before a request is granted. When a completion-required request receives a grant, it picks up the TAG ID from the storage rather than generating it on the fly. This enables the system to process back-to-back TLP requests without any dead cycles.

Abstract: A branch of CRC resources is configured to process back-to-back TLPs in a PCIe architecture. A state machine receives back-to-back TLPs and generates carrier signals, which it then routes to the branch of CRC resources. These signals are used to align the back-to-back TLPs such that a LCRC for each of the back-to-back TLPs is calculated by the branch of CRC resources at line speed. The system and method allow substantial gate-count savings to be realized, as the present invention minimizes the number of components necessary to achieve the desired results.

Abstract: A method for minimizing compilation time of a test case during development testing of an integrated circuit is provided. The method initiates with identifying a test case. The test case is associated with the tasks and the tasks are written as text files. Then, a file associated with the test case is generated. Next, a sequence of the tasks of the file is determined. Then, hardware description language (HDL) tasks, associated with the tasks of the file according to the sequence, are identified. Next, a simulation of an integrated circuit is performed through the HDL tasks. A computer readable medium having program instructions for minimizing compilation time of a test case during development testing of an integrated circuit and a system for testing an integrated circuit design are also provided.

Abstract: The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

Abstract: The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.