Patents by Inventor Purnima Narayanan

Purnima Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020759
    Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Purnima Narayanan
  • Publication number: 20210358951
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Publication number: 20210327898
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Application
    Filed: May 24, 2021
    Publication date: October 21, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Publication number: 20210313346
    Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.
    Type: Application
    Filed: June 15, 2021
    Publication date: October 7, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Purnima Narayanan, Jordan D. Greenlee
  • Patent number: 11107831
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Patent number: 11056505
    Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Purnima Narayanan, Jordan D. Greenlee
  • Patent number: 11037956
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Publication number: 20210175249
    Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Purnima Narayanan, Jordan D. Greenlee
  • Publication number: 20210167081
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Patent number: 10879259
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Publication number: 20200373325
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Publication number: 20200321351
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Patent number: 10790290
    Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: David A. Daycock, Purnima Narayanan, John Hopkins, Guoxing Duan, Barbara L. Casey, Christopher J. Larsen, Meng-Wei Kuo, Qian Tao
  • Patent number: 10777576
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Publication number: 20190131315
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Application
    Filed: September 17, 2018
    Publication date: May 2, 2019
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatam Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Publication number: 20190103410
    Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: DAVID A. DAYCOCK, PURNIMA NARAYANAN, JOHN HOPKINS, GUOXING DUAN, BARBARA L. CASEY, CHRISTOPHER J. LARSEN, MENG-WEI KUO, QIAN TAO
  • Patent number: 10134758
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Patent number: 10090317
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Publication number: 20180130819
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 10, 2018
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Patent number: 9741734
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil