Patents by Inventor PURU Howard Shieh

PURU Howard Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12112669
    Abstract: A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: October 8, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Fen Tsai, Chen-Yun Ma, Puru Howard Shieh, Chih-Ching Wang
  • Publication number: 20230352452
    Abstract: A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.
    Type: Application
    Filed: April 7, 2023
    Publication date: November 2, 2023
    Inventors: Shu-Fen TSAI, Chen-Yun MA, Puru Howard SHIEH, Chih-Ching WANG
  • Publication number: 20220244611
    Abstract: An electrophoretic display device includes a backplane structure, a buffer layer, a spacer wall, a display medium, an upper substrate and an upper electrode. The backplane structure includes a lower substrate, a transistor formed on the lower substrate, and a lower electrode electrically connected to the transistor. The buffer layer is disposed on the backplane structure. The spacer wall is disposed on the buffer layer and forms a closed pattern. The display medium is disposed in the closed pattern. The display medium includes an electrophoretic medium and a plurality of electrophoretic particles dispersed in the electrophoretic medium. The upper substrate is disposed on the spacer wall and the display medium. The upper electrode is disposed between the upper substrate and the spacer wall.
    Type: Application
    Filed: January 14, 2022
    Publication date: August 4, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Shu-Fen TSAI, Hsien-Yi HSIAO, Ming-Kai CHUANG, Puru Howard SHIEH
  • Patent number: 9990904
    Abstract: A pixel array including first signal lines, second signal lines, active elements, pixel electrodes and selection lines is provided. The second signal lines and the selection lines are intersected with the first signal lines respectively. Each first signal line has a bridge point at an intersection with the one of the selection lines. At least one of the selection lines is disposed between two neighboring second signal lines. Amounts of the first signal lines and the selection lines are larger than an amount of the second signal lines respectively, and an amount of second signal lines intersected with a connection line between the bridge point of the ith first signal line and the bridge point of the (i+1)th first signal line is one, i=1 to N, and N is the amount of the first signal lines.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 5, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Ya-Chen Huang, Puru Howard Shieh, Ni-Yeh Wu, Pei-Lin Huang, Chi-Ming Wu
  • Publication number: 20170110091
    Abstract: A pixel array including first signal lines, second signal lines, active elements, pixel electrodes and selection lines is provided. The second signal lines and the selection lines are intersected with the first signal lines respectively. Each first signal line has a bridge point at an intersection with the one of the selection lines. At least one of the selection lines is disposed between two neighbouring second signal lines. Amounts of the first signal lines and the selection lines are larger than an amount of the second signal lines respectively, and an amount of second signal lines intersected with a connection line between the bridge point of the ith first signal line and the bridge point of the (i+1)th first signal line is one, i=1 to N, and N is the amount of the first signal lines.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Applicant: E Ink Holdings Inc.
    Inventors: Ya-Chen Huang, PURU Howard Shieh, Ni-Yeh Wu, Pei-Lin Huang, Chi-Ming Wu