Patents by Inventor Purushothaman Nandakumaran

Purushothaman Nandakumaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133012
    Abstract: A networking device uses multipath routing for paths designated as logical paths having associated physical interfaces, such that link down events are processed by remapping related logical paths to other physical links. The networking device includes a forwarding table that is generated according to a multipath algorithm, such as an equal-cost multipath (ECMP) algorithm. The forwarding table specifies different logical paths mapped to physical links, which may include different physical interfaces and related processing information. Packets are processed by selecting a logical path and applying the mapped profile information and/or physical egress interface of the selected logical path. When a link down monitor detects a link down event, a logical path mapped to the now-unavailable physical link is remapped to another physical link, enabling packets to be selected for the affected logical path and successfully processed before re-calculation of forwarding table to account for the unavailable physical link.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: Arista Networks, Inc.
    Inventors: Purushothaman Nandakumaran, Terence King Lam Hui
  • Patent number: 12278713
    Abstract: Malformed VLAN packets can be detected by programming suitable rules in a TCAM in the packet processing pipeline. In some deployments, for example, the TCAM rule(s) can match on the parsed EtherType metadata. More specifically, the match can be based on the EtherType metadata being set to a value equal to known VLAN TPIDs, such as 0x8100, 0x88a8, rather than being set to a standard EtherType.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 15, 2025
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Anirudh Ramesh Iyer, Satish Kumar Selvaraj, Akhil Ojha, Purushothaman Nandakumaran, Aman Aman-Ul-Haq, Jyothish Kunkumath
  • Publication number: 20240121188
    Abstract: Software tables in the control plane of a network device are downloaded into the data plane hardware after a reboot of the control plane. Valid entries are identified and downloaded while reducing the downloading invalid or otherwise unused entries to improve download times and reduce disruption of traffic resulting from the download. In some instances, blocks of entries containing a high ratio of valid to invalid entries are identified and downloaded to the hardware. In some instances, entries in the software tables that differ from corresponding entries in the hardware (diff entries) are identified and downloaded. In some instances, chunks containing diff entries and non-diff entries are identified and downloaded.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Lakshmikantha Chowdary Pothula, Purushothaman Nandakumaran, Swaroop George, Ravil Baizhiyenov, Jiacheng Guo, Zhong Xu
  • Publication number: 20240121151
    Abstract: Software tables in the control plane of a network device are downloaded into the data plane hardware after a reboot of the control plane. Valid entries are identified and downloaded while reducing the downloading invalid or otherwise unused entries to improve download times and reduce disruption of traffic resulting from the download. In some instances, blocks of entries containing a high ratio of valid to invalid entries are identified and downloaded to the hardware. In some instances, entries in the software tables that differ from corresponding entries in the hardware (diff entries) are identified and downloaded. In some instances, chunks containing diff entries and non-diff entries are identified and downloaded.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Lakshmikantha Chowdary Pothula, Swaroop George, Purushothaman Nandakumaran, Joseph Olakangil, Sandeep Gawai
  • Patent number: 11881935
    Abstract: In general, embodiments relate to a method, for managing a network device, that includes accessing, by a feature agent of the network device, an allocation data structure, wherein the allocation data structure specifies a first portion of memory and a second portion of memory, identifying, using the allocation data structure, the first portion of the memory to be used during an upgrade, wherein the second portion of memory is used for storing a network device table, wherein the network device table is used by a packet transmission component while the upgrade is being performed, and upon completion of the upgrade, updating the allocation data structure to specify that the packet transmission component use a second network device table and stop using the network device table, wherein the second network device table is initially populated during the upgrade.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: January 23, 2024
    Assignee: Arista Networks, Inc.
    Inventors: Purushothaman Nandakumaran, Joseph Olakangil, Lakshmikanth Chowdary Pothula, Swaroop George
  • Patent number: 11799780
    Abstract: Systems and methods are provided herein for implementing multi-table OpenFlow flows that have combinations of packet edits. This may be accomplished by a network device receiving a first flow entry with a first set of actions to be installed into a flow table. The network device may determine that the first set of actions includes edits to a plurality of fields of a matched data packet. In response, the network device may change the first set of actions of the first flow entry to edit a first field of the data packet and create a second flow entry with a second set of actions to edit a second field of the data packet. The network device may install the first and second flow entries into one or more flow tables of the network device.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: October 24, 2023
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Joseph Olakangil, Nitin Karkhanis, Anuraag Mittal, Purushothaman Nandakumaran, Manjula Gopalakrishnan
  • Publication number: 20230283574
    Abstract: In general, embodiments relate to a method, for managing a network device, that includes accessing, by a feature agent of the network device, an allocation data structure, wherein the allocation data structure specifies a first portion of memory and a second portion of memory, identifying, using the allocation data structure, the first portion of the memory to be used during an upgrade, wherein the second portion of memory is used for storing a network device table, wherein the network device table is used by a packet transmission component while the upgrade is being performed, and upon completion of the upgrade, updating the allocation data structure to specify that the packet transmission component use a second network device table and stop using the network device table, wherein the second network device table is initially populated during the upgrade.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Inventors: Purushothaman Nandakumaran, Joseph Olakangil, Lakshmikant Chowdary Pothula, Swaroop George
  • Publication number: 20230147422
    Abstract: Malformed VLAN packets can be detected by programming suitable rules in a TCAM in the packet processing pipeline. In some deployments, for example, the TCAM rule(s) can match on the parsed EtherType metadata. More specifically, the match can be based on the EtherType metadata being set to a value equal to known VLAN TPIDs, such as 0x8100, 0x88a8, rather than being set to a standard EtherType.
    Type: Application
    Filed: December 29, 2021
    Publication date: May 11, 2023
    Inventors: Anirudh Ramesh Iyer, Satish Kumar Selvaraj, Akhil Ojha, Purushothaman Nandakumaran, Aman Aman-Ul-Haq, Jyothish Kunkumath
  • Patent number: 11632445
    Abstract: Techniques for operating a network device for multiple packet encapsulation for different tunnels are provided. In some embodiments, the network device may receive an original packet on an ingress port, the original packet being received from a first host and addressed to a second host; encapsulate the original packet in a first tunnel packet for a first tunnel; recirculate the first packet through a loopback port; encapsulate the recirculated packet in a second tunnel packet for a second tunnel; and egress the packet encapsulated for the second tunnel. The switch may further add a first tunnel header to the original packet to encapsulate the first packet and add a second tunnel header to the recirculated packet to encapsulate the recirculated packet.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: April 18, 2023
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Purushothaman Nandakumaran, Munisha Rani
  • Publication number: 20230114898
    Abstract: Methods, systems, and apparatuses for efficient tracking and exporting of network flows using custom filters. A network device receives network data and classifies a flow of the network data as belonging to a defined flow group from among a plurality of defined flow groups. A set of rules is identified that correspond to the defined flow group. Flow information is updated for a characteristic of the flow according to the set of rules. The network device determines, based on the flow information, that the flow satisfies a set of criteria involving the characteristic and, as a result of the determination, controls transmission of data associated with the flow.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 13, 2023
    Inventors: Jeevan Kamisetty, Ripon Bhattacharjee, Purushothaman Nandakumaran, Utkarsha Verma, Zhe Wang
  • Publication number: 20220303364
    Abstract: Techniques for operating a network device for multiple packet encapsulation for different tunnels are provided. In some embodiments, the network device may receive an original packet on an ingress port, the original packet being received from a first host and addressed to a second host; encapsulate the original packet in a first tunnel packet for a first tunnel; recirculate the first packet through a loopback port; encapsulate the recirculated packet in a second tunnel packet for a second tunnel; and egress the packet encapsulated for the second tunnel. The switch may further add a first tunnel header to the original packet to encapsulate the first packet and add a second tunnel header to the recirculated packet to encapsulate the recirculated packet.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventors: Purushothaman Nandakumaran, Munisha Rani
  • Publication number: 20220131801
    Abstract: Systems and methods are provided herein for implementing multi-table OpenFlow flows that have combinations of packet edits. This may be accomplished by a network device receiving a first flow entry with a first set of actions to be installed into a flow table. The network device may determine that the first set of actions includes edits to a plurality of fields of a matched data packet. In response, the network device may change the first set of actions of the first flow entry to edit a first field of the data packet and create a second flow entry with a second set of actions to edit a second field of the data packet. The network device may install the first and second flow entries into one or more flow tables of the network device.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Inventors: Joseph Olakangil, Nitin Karkhanis, Anuraag Mittal, Purushothaman Nandakumaran, Manjula Gopalakrishnan
  • Patent number: 11245624
    Abstract: Systems and methods are provided herein for implementing multi-table OpenFlow flows that have combinations of packet edits. This may be accomplished by a network device receiving a first flow entry with a first set of actions to be installed into a flow table. The network device may determine that the first set of actions includes edits to a plurality of fields of a matched data packet. In response, the network device may change the first set of actions of the first flow entry to edit a first field of the data packet and create a second flow entry with a second set of actions to edit a second field of the data packet. The network device may install the first and second flow entries into one or more flow tables of the network device.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: February 8, 2022
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Joseph Olakangil, Nitin Karkhanis, Anuraag Mittal, Purushothaman Nandakumaran, Manjula Gopalakrishnan
  • Publication number: 20210344599
    Abstract: Systems and methods are provided herein for implementing multi-table OpenFlow flows that have combinations of packet edits. This may be accomplished by a network device receiving a first flow entry with a first set of actions to be installed into a flow table. The network device may determine that the first set of actions includes edits to a plurality of fields of a matched data packet. In response, the network device may change the first set of actions of the first flow entry to edit a first field of the data packet and create a second flow entry with a second set of actions to edit a second field of the data packet. The network device may install the first and second flow entries into one or more flow tables of the network device.
    Type: Application
    Filed: May 1, 2020
    Publication date: November 4, 2021
    Inventors: Joseph Olakangil, Nitin Karkhanis, Anuraag Mittal, Purushothaman Nandakumaran, Manjula Gopalakrishnan
  • Patent number: 9876739
    Abstract: A system and method of failure detection in rings includes a switch including a control unit, one or more first ports coupled to the control unit and configured to couple the switch to a ring of switches in a first direction, and one or more second ports coupled to the control unit and configured to couple the switch to the ring of switches in a second direction opposite the first direction. The control unit is configured to detect a failure in the ring of switches in the second direction, transmit a request message in the first direction using one of the one or more first ports, receive a response message on one of the one or more first ports, extract reachability data from the response message, and determine one or more first switches in the ring of switches that are reachable in the first direction based on information associated with the reachability data.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 23, 2018
    Assignee: DELL PRODUCTS L.P.
    Inventors: Ravikumar Sivasankar, Purushothaman Nandakumaran, Joyas Joseph, William Zengli Yu
  • Patent number: 9660901
    Abstract: A first switch forms first and second LAGs and a main LAG comprising the first and second LAGs as sub-LAGs. Forming the first and second LAGs comprises receiving LACP data units which indicate that the first switch is connected to second and third switches through first and second pluralities of ports, and forming the first LAG of the first plurality of ports and the second LAG of the second plurality of ports. The second and third switches share a control plane. In forming the first and second LAGs, LACP data units are received from the second and third switches and include unique identifiers of the second and third switches respectively. Forming the main LAG comprises receiving one or more LACP data units which indicate that the first and second plurality of ports are to be part of the main LAG, and forming the main LAG based on such LACP data units. Other features are also provided.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: May 23, 2017
    Assignee: Dell Products L.P.
    Inventors: Ravikumar Sivasankar, Purushothaman Nandakumaran
  • Publication number: 20140359364
    Abstract: A system and method of failure detection in rings includes a switch including a control unit, one or more first ports coupled to the control unit and configured to couple the switch to a ring of switches in a first direction, and one or more second ports coupled to the control unit and configured to couple the switch to the ring of switches in a second direction opposite the first direction. The control unit is configured to detect a failure in the ring of switches in the second direction, transmit a request message in the first direction using one of the one or more first ports, receive a response message on one of the one or more first ports, extract reachability data from the response message, and determine one or more first switches in the ring of switches that are reachable in the first direction based on information associated with the reachability data.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Ravikumar Sivasankar, Purushothaman Nandakumaran, Joyas Joseph, William Zengli Yu
  • Publication number: 20140133486
    Abstract: An information handling system is provided. The information handling system includes a first switch that has a computer processor in communication with a plurality of ports for receiving and sending packets and a memory including a look-up table. The look-up table associates at least some of the plurality of ports with a group of link aggregation groups (LAGs) such that an incoming packet is received by the first switch as belonging to a first LAG of the group of LAGs and an outgoing packet is sent out from the switch as belonging to either the first LAG or a second LAG of the group of LAGs depending on a type of the outgoing packet. Methods for forming and using a group of LAGs to reduce traffic on interconnect links are also provided.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: Dell Products L.P.
    Inventors: Ravikumar Sivasankar, Purushothaman Nandakumaran
  • Patent number: 8625407
    Abstract: A virtual chassis includes two or more physical chassis and operates as a single, logical device. Each of the two or more physical chassis include two route processor modules (RPM) and each RPM is assigned a first and a second role within the virtual chassis. The first role is a physical chassis level role and the second role is a virtual chassis level role. The RPMs operate in coordination such that the failure of any one of the RPMs results in one or more other RPMs taking over the first and second roles of the failed RPM.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: January 7, 2014
    Assignee: Force10 Networks, Inc.
    Inventors: Janardhanan P. Narasimhan, Sanjeev Agrawal, Purushothaman Nandakumaran, Joyas Joseph
  • Publication number: 20120063299
    Abstract: A virtual chassis includes two or more physical chassis and operates as a single, logical device. Each of the two or more physical chassis include two route processor modules (RPM) and each RPM is assigned a first and a second role within the virtual chassis. The first role is a physical chassis level role and the second role is a virtual chassis level role. The RPMs operate in coordination such that the failure of any one of the RPMs results in one or more other RPMs taking over the first and second roles of the failed RPM.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 15, 2012
    Applicant: Force10 Networks, Inc.
    Inventors: Janardhanan P. Narasimhan, Sanjeev Agrawal, Purushothaman Nandakumaran, Joyas Joseph