Patents by Inventor Purushothaman SRINIVASAN

Purushothaman SRINIVASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220334849
    Abstract: The present invention extends to methods, systems, and computer program products for automating DevOps toolchains. A user registers with a platform provider through a user interface that provides a unified self-service portal. Subsequently, the user can login to a platform configuration system to access a user landing page and/or dashboard. The user can select DevOps platform tools to be installed and enter configuration information. When the user is satisfied with selected DevOps platform tools and entered configuration, the user can select a “confirm” user-interface control (e.g., a button). In response, the selected DevOps tools are installed (with a relatively high level of automation) as DevOps platform. The user can also change DevOps platforms through the user interface (also with a relatively high level of automation), including migrating, deleting, and upgrading DevOps tools.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 20, 2022
    Inventors: Ravi Kumar Chivukula, Chandra Rananathan, Vasanthavishnu Vasudevan, Sundar Rajan Renganathan, Todd Barczak, Purushothaman Srinivasan
  • Patent number: 11474835
    Abstract: The present invention extends to methods, systems, and computer program products for replacing DevOps tools in DevOps toolchains. A user selection of a replacement DevOps platform tool associated with a DevOps platform category is received. Configuration information for the DevOps platform, including cloud service provider profile information and existing tool profile information is accessed. The existing tool is removed from the DevOps platform in accordance with the existing tool profile information, the DevOps platform category, and the service provider profile information. A replacement tool and replacement tool profile information are accessed. The replacement tool is deployed to the DevOps platform in accordance with the replacement tool profile information, the DevOps platform category, and the cloud service provider profile information.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 18, 2022
    Assignee: Opsera Inc.
    Inventors: Ravi Kumar Chivukula, Chandra Ranganathan, Vasanthavishnu Vasudevan, Todd Barczak, Sundar Rajan Renganathan, Purushothaman Srinivasan
  • Patent number: 11416266
    Abstract: The present invention extends to methods, systems, and computer program products for automating DevOps toolchains. A user registers with a platform provider through a user interface that provides a unified self-service portal. Subsequently, the user can login to a platform configuration system to access a user landing page and/or dashboard. The user can select DevOps platform tools to be installed and enter configuration information. When the user is satisfied with selected DevOps platform tools and entered configuration, the user can select a “confirm” user-interface control (e.g., a button). In response, the selected DevOps tools are installed (with a relatively high level of automation) as DevOps platform. The user can also change DevOps platforms through the user interface (also with a relatively high level of automation), including migrating, deleting, and upgrading DevOps tools.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 16, 2022
    Assignee: Opsera Inc.
    Inventors: Ravi Kumar Chivukula, Chandra Ranganathan, Vasanthavishnu Vasudevan, Sundar Rajan Renganathan, Todd Barczak, Purushothaman Srinivasan
  • Publication number: 20220121478
    Abstract: The present invention extends configuring development and operations pipelines using drag and drop techniques. Through user interface gestures, users can form and manage pipelines that span any combination of: public cloud resources, private cloud resources, user on-premise resources, etc., in accordance with appropriate (cloud and/or on-premise) profile information. The user interface facilitates pipeline (re)configuration as appropriate to address alterations to workflows, upgrades to DevOps tools, removal of functionality from a workflow, etc. The user interface enables customers to build no-code pipelines for various use cases in a drag and drop manner. Users can integrate collaboration tools, notifications, and approval gates offering thresholds at each and every step. In addition, the pipeline framework captures logs and provides a summary via livestream and also upon completion of each pipeline activity and after each pipeline.
    Type: Application
    Filed: March 25, 2021
    Publication date: April 21, 2022
    Inventors: Ravi Kumar Chivukula, Chandra Ranganathan, Todd Barczak, Sundar Rajan Renganathan, Vasanthavishnu Vasudevan, Purushothaman Srinivasan
  • Publication number: 20220091857
    Abstract: The present invention extends to methods, systems, and computer program products for replacing DevOps tools in DevOps toolchains. A user selection of a replacement DevOps platform tool associated with a DevOps platform category is received. Configuration information for the DevOps platform, including cloud service provider profile information and existing tool profile information is accessed. The existing tool is removed from the DevOps platform in accordance with the existing tool profile information, the DevOps platform category, and the service provider profile information. A replacement tool and replacement tool profile information are accessed. The replacement tool is deployed to the DevOps platform in accordance with the replacement tool profile information, the DevOps platform category, and the cloud service provider profile information.
    Type: Application
    Filed: March 16, 2021
    Publication date: March 24, 2022
    Inventors: Ravi Kumar Chivukula, Chandra Ranganathan, Vasanthavishnu Vasudevan, Todd Barczak, Sundar Rajan Renganathan, Purushothaman Srinivasan
  • Publication number: 20220091854
    Abstract: The present invention extends to methods, systems, and computer program products for automating DevOps toolchains. A user registers with a platform provider through a user interface that provides a unified self-service portal. Subsequently, the user can login to a platform configuration system to access a user landing page and/or dashboard. The user can select DevOps platform tools to be installed and enter configuration information. When the user is satisfied with selected DevOps platform tools and entered configuration, the user can select a “confirm” user-interface control (e.g., a button). In response, the selected DevOps tools are installed (with a relatively high level of automation) as DevOps platform. The user can also change DevOps platforms through the user interface (also with a relatively high level of automation), including migrating, deleting, and upgrading DevOps tools.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 24, 2022
    Inventors: Ravi Kumar Chivukula, Chandra Ranganathan, Vasanthavishnu Vasudevan, Sundar Rajan Renganathan, Todd Barczak, Purushothaman Srinivasan
  • Publication number: 20160343806
    Abstract: Methods for fabricating interface passivation layers in a circuit structure are provided. The method includes forming a silicon-germanium layer over a substrate, removing a native oxide layer from an upper surface of the silicon-germanium layer, and exposing the upper surface of the silicon-germanium layer to an ozone-containing solution, resulting in an interface passivation layer with a higher concentration of germanium-dioxide present than germanium-oxide. The resulting interface passivation layer may be part of a gate structure, in which the channel region of the gate structure includes the silicon-germanium layer and the interface passivation layer between the channel region and the dielectric layer of the gate structure has a high concentration of germanium-dioxide.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 24, 2016
    Applicants: GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shariq SIDDIQUI, Jody A. FRONHEISER, Murat Kerem AKARVARDAR, Purushothaman SRINIVASAN, Lisa F. EDGE, Gangadhara Raja MUTHINTI, Georges JACOBI, Randolph KNARR
  • Patent number: 8753938
    Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 17, 2014
    Assignee: Texes Instruments Incorporated
    Inventors: Alwin James Tsao, Purushothaman Srinivasan
  • Publication number: 20140120674
    Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Alwin James TSAO, Purushothaman SRINIVASAN
  • Patent number: 8653607
    Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Alwin James Tsao, Purushothaman Srinivasan
  • Publication number: 20120319210
    Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 20, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alwin James TSAO, Purushothaman SRINIVASAN