Patents by Inventor Purval Shyam Sule

Purval Shyam Sule has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714186
    Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Purval Shyam Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Ramkrishna Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky
  • Publication number: 20190304543
    Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.
    Type: Application
    Filed: March 4, 2019
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Purval Shyam Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Ramkrishna Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky
  • Patent number: 10268407
    Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval Shyam Sule
  • Publication number: 20190102097
    Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval Shyam Sule
  • Patent number: 10224107
    Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Purval Shyam Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Ramkrishna Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky