Patents by Inventor Pushkal Yadav

Pushkal Yadav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7613213
    Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: November 3, 2009
    Assignee: Transwitch Corporation
    Inventors: Pushkal Yadav, Kumar Shakti Singh, Chitra Wadhwa, Sachin Mathur, Ashis Maitra, Amandeep Singh Gujral, Diljit Singh, Yudhishthira Kundu
  • Publication number: 20060039416
    Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.
    Type: Application
    Filed: August 23, 2005
    Publication date: February 23, 2006
    Inventors: Pushkal Yadav, Kumar Singh, Chitra Wadhwa, Sachin Mathur, Ashis Maitra, Amandeep Gujral, Diljit Singh
  • Publication number: 20060039400
    Abstract: Whenever a PAUSE frame is generated locally, a pause refresh timer is set with the pause parameter from the PAUSE frame. PAUSE frames which are received from a remote data sink are trapped and the value of the pause parameter is evaluated. If the value is smaller than the current pause refresh timer value, the pause frame is discarded. If the value is equal to or larger than the current pause refresh timer value, the PAUSE frame is passed on to the data source and an end-to-end flow control (EEFC) timer is set with the pause parameter received from the remote data sink. While the EEFC timer is counting down, locally generated PAUSE frames having a pause parameter less than the timer value are suppressed.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Inventors: Suvhasis Mukhopadhyay, Pushkal Yadav, Neil Singer, Ramakrishnan Shankar
  • Patent number: 6539023
    Abstract: An apparatus for handling back-to-back maintenance messages in extended superframe t1 telephone circuits includes a FIFO, a byte counter, and a message length register. According toga method of the invention, when messages are placed in the. FIFO, the byte counter counts the message length and places the message length in the message length register. A host controller is required to read the message length register in the time interval following complete receipt of a first message before complete receipt of a second message, but is only required to read the contents of the FIFO before it overflows. According to a presently preferred embodiment of the apparatus, a second register is provided for indicating the current depth of the FIFO. The second register sends an interrupt to the host controller when the contents of the FIFO exceed a threshold.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: March 25, 2003
    Assignee: Transwitch Corporation
    Inventors: William G. Bartholomay, Santanu Bhattacharya, Pushkal Yadav, Balaraj Vishnu Varthanan
  • Patent number: 6456595
    Abstract: A method and apparatus for reliably detecting both AIS and AIS-CI signals in the presence of a bit error ratio up to 1×10−3 includes an AIS detector having an AIS indication output, a CI detector having a CI indication output, and a two signal AND gate having its inputs coupled to the respective outputs of the detectors and having an output indicative of an AIS-CI detection. The AIS detector has an adjustable zero threshold and the CI detector has a threshold output coupled to the AIS detector for adjusting the zero threshold. According to the method of the invention, the AIS detector zero threshold is normally set at the normal threshold (1×10−3) but is reset to a higher threshold (e.g., 2×10−3) when the CI detector detects the presence of the CI code word.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: September 24, 2002
    Assignee: Transwitch Corporation
    Inventors: William G. Bartholomay, Santanu Bhattacharya, Pushkal Yadav, Balaraj Vishnu Varthanan