Patents by Inventor Pushkar P. Apte

Pushkar P. Apte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6317640
    Abstract: Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: November 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Suraj Rao, Sharad Saxena, Pushkar P. Apte, Purnendu K. Mozumder, Richard Gene Burch, Karthik Vasanth, Joseph Carl Davis, Chenjing L. Fernando
  • Patent number: 5593924
    Abstract: A titanium-silicide process using a capping layer to reduce the silicide sheet resistance. A layer of titanium (20) is deposited. A react capping layer (22) may then be deposited to prevent contaminants from entering the titanium layer (20)during the subsequent react step. The layer of titanium (20) is then reacted to form titanium-silicide (32). The react capping layer (22) is then removed and an anneal capping layer (36) is deposited to prevent contaminants from entering the silicide layer (32) during the subsequent anneal step. Then, the silicide anneal is performed to accomplish to transformation to a lower resistivity phase of silicide. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: January 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Pushkar P. Apte, Ajit P. Paranjpe