Patents by Inventor Pushkar U. Mokashi

Pushkar U. Mokashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • No latency pipeline
    Patent number: 5532970
    Abstract: An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: July 2, 1996
    Inventors: Edward Butler, Martin B. Lundberg, Pushkar U. Mokashi, Alfred L. Sartwell, Hemen R. Shah, Robert Tamlyn