Abstract: A transistor includes one or more orthogonal inner spacers. The orthogonal inner spacer may include a vertical portion and a horizontal base portion that extends inwardly beyond a plane that is coplanar with a sidewall of the gate. The horizontal base portion(s) may reduce the gate length of the gate adjacent to the horizontal base portion(s). The orthogonal inner spacers may result in reduced parasitic capacitances between gate and the substrate and/or between the gate and adjacent source/drain region(s), and/or may reduce current leakage from the gate into the substrate or other underlying structure.

Abstract: Embodiments of the disclosure include a semiconductor structure having channel regions stacked over a substrate and connected to source/drain regions. The semiconductor structure includes a buffer layer intervening between the channel regions and the source/drain regions and inner spacers formed in part of the buffer layer.

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.