Patents by Inventor Pushpendra KUMAR

Pushpendra KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260064462
    Abstract: In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 5, 2026
    Applicant: Intel Corporation
    Inventors: Pushpendra Kumar, Amruta Misra, Niall McDonnell, Ambalavanar Arulambalam, Ximing Chen, Paul Beatty, Pravin Pathak
  • Patent number: 12556597
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: February 17, 2026
    Assignee: Intel Corporation
    Inventors: Amruta Misra, Niall McDonnell, Mrittika Ganguli, Edwin Verplanke, Stephen Palermo, Rahul Shah, Pushpendra Kumar, Vrinda Khirwadkar, Valerie Parker
  • Publication number: 20250206610
    Abstract: The present invention relates to the working principle and production methods for the pre-expansion of sulfur and/or other chalcogenides such as selenium or tellurium, and/or a mixture of any two or more. The present invention further relates an electrode/cathode comprising sulfur and/or a mixture of sulfur allotropes, for example, crystalline, glassy, amorphous, and/or polymeric (e.g., ?-, ?-, and/or ?-phasic) sulfur and/or a mixture of any two or more sulfur allotropes, wherein the sulfur is photonically/electronically/thermally pre-expanded to a state where it has a density equivalent to a metal sulfide, such as Li2S. The expansion is carried out before electrode/cathode fabrication for the realization of alkali and/or alkali earth metal/ion batteries, such as LiS batteries.
    Type: Application
    Filed: December 18, 2024
    Publication date: June 26, 2025
    Applicant: Theion GmbH
    Inventors: Marek SLAVIK, Aamir WAIDHA, Marin PUGET, Saswat MOHANTY, Pushpendra KUMAR
  • Publication number: 20250096243
    Abstract: The present disclosure relates to a porous chalcogenide-based electrode including crystalline allotropes within the core, at least one of a glass, polymeric and amorphous chalcogenide present within the transition layer and/or a shell covering the surface of the active electrode material. The electrode includes a transition layer covalently bonded between a 2D material and the chalcogenide of the electrode material, a coating layer on top of the transition layer and including a 2D material, an electrode in which the volume of crystalline allotrope represents a buffer volume that compensates the volumetric fluctuation during battery cycling, and a chalcogenide electrode. The electrode active mass includes a dopant such as selenium and tellurium, wherein the mass content of sulfur in the cathode is above 50% per weight, wherein the coated electrode includes at least one sulfur allotrope that is doped with a chalcogenide, a halogen, or a mixture thereof.
    Type: Application
    Filed: September 17, 2024
    Publication date: March 20, 2025
    Applicant: Theion GmbH
    Inventors: Pushpendra KUMAR, Marek SLAVIK, Marin PUGET, Aamir Iqbal WAIDHA, Thomas PEHL, Andréa Joris Quentin MARTIN, Juthaporn WUTTHIPROM
  • Publication number: 20240143505
    Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Inventors: Amruta MISRA, Ajay RAMJI, Rajendrakumar CHINNAIYAN, Chris MACNAMARA, Karan PUTTANNAIAH, Pushpendra KUMAR, Vrinda KHIRWADKAR, Sanjeevkumar Shankrappa ROKHADE, John J. BROWNE, Francesc GUIM BERNAT, Karthik KUMAR, Farheena Tazeen SYEDA
  • Publication number: 20240129353
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventors: Amruta Misra, Niall McDonnell, Mrittika Ganguli, Edwin Verplanke, Stephen Palermo, Rahul Shah, Pushpendra Kumar, Vrinda Khirwadkar, Valerie Parker
  • Patent number: 10840539
    Abstract: Prelithiation of a battery anode carried out using controlled lithium metal vapor deposition. Lithium metal can be avoided in the final battery. This prelithiated electrode is used as potential anode for Li-ion or high energy Li—S battery. The prelithiation of lithium metal onto or into the anode reduces hazardous risk, is cost effective, and improves the overall capacity. The battery containing such an anode exhibits remarkably high specific capacity and a long cycle life with excellent reversibility.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 17, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Lain-Jong Li, Feng-Yu Wu, Pushpendra Kumar, Jun Ming
  • Publication number: 20190259618
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. The metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition with process parameters selected so as to produce grains of material exhibiting a uniaxial grain orientation. The uniaxial grain structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 22, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Florian Domengie, Pushpendra Kumar
  • Publication number: 20180301745
    Abstract: Prelithiation of a battery anode carried out using controlled lithium metal vapor deposition. Lithium metal can be avoided in the final battery. This prelithiated electrode is used as potential anode for Li-ion or high energy Li—S battery. The prelithiation of lithium metal onto or into the anode reduces hazardous risk, is cost effective, and improves the overall capacity. The battery containing such an anode exhibits remarkably high specific capacity and a long cycle life with excellent reversibility.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 18, 2018
    Applicant: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Lain-Jong LI, Feng-Yu WU, Pushpendra KUMAR, Jun MING