Patents by Inventor Pyeng Geun Sohn

Pyeng Geun Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a self-aligned floating gate in flash memory cell
    Patent number: 6656793
    Abstract: A method of forming a self-aligned floating gate in a flash memory cell. A capping layer is formed on a trench insulating film. An etching process is then performed to etch the trench insulating film to a desired dimension. Therefore, generation of a moat in the trench insulating film is avoided. Further, spacing of a floating gate formed in a subsequent process can be minimized.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 2, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Mo Jeong, Pyeng Geun Sohn
  • Method of forming a metal line in a semiconductor device
    Publication number: 20030119325
    Abstract: The present invention relates to a method of forming a metal line in a semiconductor device. Upon a process of forming a barrier metal layer of Ti/TiN using an ion metal plasma (IMP) method, an increased AC bias power is applied to increase a deposition thickness of Ti/TiN at an edge portion of the bottom of a contact hole. Therefore, it is possible to prevent penetration of fluorine ions into the semiconductor substrate upon a process of depositing a subsequent tungsten layer.
    Type: Application
    Filed: November 4, 2002
    Publication date: June 26, 2003
    Inventors: Cheol Mo Jeong, Pyeng Geun Sohn
  • Method of forming a self-aligned floating gate in flash memory cell
    Publication number: 20030119259
    Abstract: A method of forming a self-aligned floating gate in a flash memory cell. A capping layer is formed on a trench insulating film. An etching process is then performed to etch the trench insulating film to a desired dimension. Therefore, generation of a moat in the trench insulating film is avoided. Further, spacing of a floating gate formed in a subsequent process can be minimized.
    Type: Application
    Filed: November 27, 2002
    Publication date: June 26, 2003
    Inventors: Cheol Mo Jeong, Pyeng Geun Sohn