Abstract: In a method of manufacturing a semiconductor device, a first selective epitaxial growth (SEG) process is performed on a substrate to form a first channel. A first etching process is performed to form a first recess through the first channel and an upper portion of the substrate. A sidewall of the first channel exposed by the first recess is slanted with respect to an upper surface of the substrate. A second SEG process is performed to form a second channel on a surface of the substrate and the sidewall of the first channel exposed by the first recess. A gate structure is formed to fill the first recess. An impurity region is formed at an upper portion of the substrate adjacent to the gate structure.

Abstract: A method of manufacturing an integrated circuit device includes alternately stacking sacrificial semiconductor layers and channel layers on a substrate to form a stack structure, forming source regions and drain regions on both sides of the stack structure, forming a gate space between the channel layers by removing the sacrificial semiconductor layers, forming the channel layers to be spaced apart from each other in a perpendicular direction to the substrate, performing a plasma treatment of boron trichloride (BCL3) on the channel layers, forming gate dielectric layers on the channel layers on which the plasma treatment of boron trichloride (BCL3) is performed, and forming gate layers covering the gate dielectric layers in the gate space.

Abstract: An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: Disclosed are method and apparatus for forming a thin layer. The method for forming the thin layer comprises providing a substrate including patterns, forming a bonding layer on the substrate covering an inner surface of a gap between the patterns, forming a preliminary layer on the bonding layer filling the gap; and thermally treating the preliminary layer to form the thin layer. The bonding layer is a self-assembled monomer layer formed using an organosilane monomer. The preliminary layer is formed from a flowable composition comprising polysilane.

Abstract: Disclosed are method and apparatus for forming a thin layer. The method for forming the thin layer comprises providing a substrate including patterns, forming a bonding layer on the substrate covering an inner surface of a gap between the patterns, forming a preliminary layer on the bonding layer filling the gap; and thermally treating the preliminary layer to form the thin layer. The bonding layer is a self-assembled monomer layer formed using an organosilane monomer. The preliminary layer is formed from a flowable composition comprising polysilane.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A plasma monitoring device includes a fixing unit, a plasma measuring unit disposed to be in contact with the fixing unit, and measuring a luminous intensity of emitted light of a plasma to output a luminous intensity measurement value, a reference light source unit irradiating reference light having a uniform luminous intensity to the plasma measuring unit, and a control unit receiving the luminous intensity measurement value to calculate a luminous intensity value of the emitted light, controlling a voltage applied to the reference light source unit to uniformly control a luminous intensity of the reference light, comparing a luminous intensity of the reference light irradiated to the plasma measuring unit with a previously stored luminous intensity reference value to detect a correction factor, and applying the correction factor to a luminous intensity value of the emitted light to correct the luminous intensity measurement value.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A method of performing a surface treatment includes passivating a surface of an insulating part in a reaction chamber, and then performing a hydrogen plasma annealing treatment on a substrate in the reaction chamber. The passivation of the surface of the insulating part includes supplying a nitrogen-based gas into the reaction chamber and exciting the nitrogen-based gas in the reaction chamber using a plasma generator.

Abstract: A plasma monitoring device includes a fixing unit, a plasma measuring unit disposed to be in contact with the fixing unit, and measuring a luminous intensity of emitted light of a plasma to output a luminous intensity measurement value, a reference light source unit irradiating reference light having a uniform luminous intensity to the plasma measuring unit, and a control unit receiving the luminous intensity measurement value to calculate a luminous intensity value of the emitted light, controlling a voltage applied to the reference light source unit to uniformly control a luminous intensity of the reference light, comparing a luminous intensity of the reference light irradiated to the plasma measuring unit with a previously stored luminous intensity reference value to detect a correction factor, and applying the correction factor to a luminous intensity value of the emitted light to correct the luminous intensity measurement value.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A method of performing a surface treatment includes passivating a surface of an insulating part in a reaction chamber, and then performing a hydrogen plasma annealing treatment on a substrate in the reaction chamber. The passivation of the surface of the insulating part includes supplying a nitrogen-based gas into the reaction chamber and exciting the nitrogen-based gas in the reaction chamber using a plasma generator.

Abstract: A plasma processing apparatus includes a susceptor, a chamber housing that accommodates the susceptor and encloses a reaction space, and an annular shaped baffle plate that annularly surrounds the susceptor. The baffle plate includes a first layer that includes a conductive material and a second layer that includes a non-conductive material, and the second layer is closer to the reaction space than the first layer.

Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

Abstract: Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Abstract: Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.