Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

Abstract: Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Abstract: Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.

Abstract: Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.

Abstract: Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.

Abstract: Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.

Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.

Abstract: A voltage regulator circuit and a semiconductor memory device using the same are provided. The voltage regulator circuit regulates an input voltage to provide an output voltage. The voltage regulator circuit comprises a voltage divider to divide the output voltage, a comparator to determine whether the divided voltage is less than a reference voltage, a driver connected between the input voltage and the output voltage, and operating operate responsive to the comparator, and a controller to control the voltage divider to gradually vary the output voltage. The voltage divider includes a resistance that operates responsive to the controller and whose value varies in a binary weighted form.

Abstract: Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.

Abstract: A voltage regulator circuit and a semiconductor memory device using the same are provided. The voltage regulator circuit regulates an input voltage to provide an output voltage. The voltage regulator circuit comprises a voltage divider to divide the output voltage, a comparator to determine whether the divided voltage is less than a reference voltage, a driver connected between the input voltage and the output voltage, and operating operate responsive to the comparator, and a controller to control the voltage divider to gradually vary the output voltage. The voltage divider includes a resistance that operates responsive to the controller and whose value varies in a binary weighted form.