Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: A disclosed embodiment comprises patterning a conductor in a dielectric in a semiconductor die. The dielectric can be, for example, silicon oxide or a low-k dielectric while the conductor can comprise aluminum, copper, or a copper-aluminum alloy. Thereafter, a blanket of high permeability layer is deposited over the dielectric. The high permeability layer can comprise high permeability materials such as nickel, iron, nickel-iron alloy, or a magnetic oxide. The blanket deposition of the high permeability layer can be accomplished by, for example, a sputtering technique. After depositing the high permeability layer, a portion of the atoms or molecules in the high permeability layer is driven into the underlying dielectric to increase the permeability of the dielectric. As an example, an ion implanter using heavy ions such as silicon ions or germanium ions can be used to drive some of the atoms or molecules in the high permeability layer into the underlying dielectric.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: In an exemplary embodiment of the disclosed transformer, the transformer comprises a dielectric area. For example, the dielectric area can consist of three different dielectric layers. Also, by way of example, the dielectric area can comprise silicon dioxide or a low-k dielectric. According to the exemplary embodiment, the dielectric area is interspersed with a permeability conversion material. The permeability conversion material has a permeability higher than the permeability of the dielectric area. For example, the permeability conversion material can be nickel, iron, nickel-iron alloy, or magnetic oxide. The exemplary embodiment further comprises a first conductor and also a second conductor patterned into the dielectric area. The first and/or the second conductor can comprise copper, aluminum, or a copper-aluminum alloy. Each of the first and second conductors are made up of a number of turns which result in, respectively, the primary and secondary windings of the exemplary disclosed transformer.

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor.