Patents by Inventor Qadeer A. Khan

Qadeer A. Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9755518
    Abstract: Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mukesh Bansal, Michael McGowan, Iulian Mirea, Qadeer Khan, Troy Stockstad, Brett Walker, Todd Sutton
  • Publication number: 20170229962
    Abstract: Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.
    Type: Application
    Filed: June 10, 2016
    Publication date: August 10, 2017
    Inventors: Mukesh Bansal, Michael McGowan, Iulian Mirea, Qadeer Khan, Troy Stockstad, Brett Walker, Todd Sutton
  • Publication number: 20170133966
    Abstract: The embodiments described herein relate to an improved system and algorithm for searching for a resonant frequency of a resonant actuator where the error between the drive frequency of the LRA and the resonant frequency of the LRA is large. In one embodiment, the drive frequency of a resonant actuator is set to an initial drive frequency, which is applied to the LRA. An induced voltage on the resonant actuator crosses can then be detected crossing a threshold voltage after the drive signal is turned off. If crossing the threshold voltage is not detected, the system is configured to sweep through a plurality of drive frequencies until the induced voltage on the resonant actuator is detected crossing the threshold voltage. This can be accomplished by repeatedly adjusting the drive frequency by a predefined incremental frequency ?F and determining when the induced voltage on the LRA crosses the threshold voltage.
    Type: Application
    Filed: November 9, 2015
    Publication date: May 11, 2017
    Inventors: Qadeer Khan, Sandeep Dhar
  • Patent number: 9442140
    Abstract: Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Mukesh Bansal, Qadeer A Khan, Chunlei Shi
  • Patent number: 9344022
    Abstract: The present disclosure includes circuits and methods for driving resonant actuators. In one embodiment, a drive signal is applied to an actuator during a portion of a plurality of half cycles of a period of the drive signal. The actuator has a resonant frequency and may vibrate in response to the drive signal. An induced voltage is generated on terminals of the actuator in response to the vibration. A detection circuit may detect when the induced voltage on the actuator crosses a threshold after the drive signal is turned off. The drive signal may be triggered based on when the induced voltage crosses the threshold to align a frequency and phase of the drive signal with the resonant frequency and a phase of the actuator.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Qadeer A Khan, Sandeep Chaman Dhar, Joshua A Zazzera, Todd R Sutton
  • Publication number: 20150263614
    Abstract: Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Mukesh BANSAL, Qadeer A KHAN, Chunlei SHI
  • Publication number: 20150069939
    Abstract: The present disclosure includes circuits and methods for driving resonant actuators. In one embodiment, a drive signal is applied to an actuator during a portion of a plurality of half cycles of a period of the drive signal. The actuator has a resonant frequency and may vibrate in response to the drive signal. An induced voltage is generated on terminals of the actuator in response to the vibration. A detection circuit may detect when the induced voltage on the actuator crosses a threshold after the drive signal is turned off. The drive signal may be triggered based on when the induced voltage crosses the threshold to align a frequency and phase of the drive signal with the resonant frequency and a phase of the actuator.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Qadeer A. Khan, Sandeep Chaman Dhar, Joshua A. Zazzera, Todd R. Sutton
  • Patent number: 7495465
    Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
  • Patent number: 7446592
    Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 4, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Tripathi, Siddhartha Gk, Qadeer A. Khan, Kulbhushan Misri, Sanjay K Wadhwa
  • Patent number: 7432748
    Abstract: A power-on reset (“POR”) methodology and circuit for an electronic circuit using multiple supply voltage domains asserts a reset signal upon ramp up of the first supply voltage signal, maintains the reset signal until all of the supply voltage signals have ramped up, and de-asserts the reset signal after all of the supply voltage signals have ramped up. Practical embodiments of the POR circuit include a control circuit that reduces static and/or dynamic current leakage associated with the operation of the POR circuit.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc
    Inventors: Qadeer A. Khan, Siddhartha Gk
  • Patent number: 7414462
    Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: August 19, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Tripathi, Jaideep Banerjee, Qadeer A. Khan
  • Patent number: 7400172
    Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 15, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjay Gupta, Qadeer A. Khan
  • Patent number: 7388419
    Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 17, 2008
    Assignee: Freescale Semiconductor, Inc
    Inventors: Siddhartha Gk, Qadeer A. Khan, Divya Tripathi, Sanjay K Wadhwa, Kulbhushan Misri
  • Patent number: 7388422
    Abstract: A charge pump circuit for a high side drive circuit and a driver driving voltage circuit that stably output a voltage when input voltage is low. The charge pump circuit includes first and second transistors, first and second capacitors, and first to third diodes. The first capacitor has a high voltage side, connected to a load driving power supply voltage via the first diode, and a low voltage side, connected to the load driving power supply voltage via the first transistor or grounded via the second transistor driven in synchronization with the first transistor. The high voltage side is supplied, via the third diode, with a low side drive voltage that is as an output voltage of a low side charge pump, and functions to output high side drive voltage to a high side pre-driver circuit via the second diode.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: June 17, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qadeer A. Khan, Hidetaka Fukazawa, Tushar S. Nandurkar
  • Publication number: 20080088340
    Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.
    Type: Application
    Filed: September 6, 2007
    Publication date: April 17, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sanjay GUPTA, Qadeer A. Khan
  • Publication number: 20070279125
    Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.
    Type: Application
    Filed: May 30, 2006
    Publication date: December 6, 2007
    Inventors: Divya Tripathi, Jaideep Banerjee, Qadeer A. Khan
  • Patent number: 7292073
    Abstract: A transmission line driver circuit that operates at a first voltage level is fabricated using devices that operate at a second, lower voltage level. The driver circuit includes a ramp generator that receives a speed signal and a data signal and generates a charge ramp signal and a discharge ramp signal. A pair of series connected source follower transistors have their gates connected to respective charge and discharge signal outputs of the ramp generator. The driver circuit output signal is generated at an output node between the sources of the NMOS and PMOS source follower transistors. A charge_ls generator circuit provides a charge_ls signal and a discharge_ls generator circuit provides a discharge_ls signal. A pair of protection transistors includes a first NMOS protection transistor and a first PMOS protection transistor, which are connected in series with respective ones of the source follower transistors, and their gates are connected to respective ones of the charge and discharge signals.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: November 6, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qadeer A. Khan, Divya Tripathi
  • Publication number: 20070080726
    Abstract: A power-on reset (“POR”) methodology and circuit for an electronic circuit using multiple supply voltage domains asserts a reset signal upon ramp up of the first supply voltage signal, maintains the reset signal until all of the supply voltage signals have ramped up, and de-asserts the reset signal after all of the supply voltage signals have ramped up. Practical embodiments of the POR circuit include a control circuit that reduces static and/or dynamic current leakage associated with the operation of the POR circuit.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 12, 2007
    Applicant: Freescale Semiconductor
    Inventors: Qadeer Khan, Siddhartha GK
  • Patent number: 7187197
    Abstract: A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 6, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Tripathi, Qadeer A. Khan, Kulbhushan Misri
  • Publication number: 20070018864
    Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: Qadeer Khan, Sanjay Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri