Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first and a second end separated by a programmable link. The first end of the one-time programmable element is coupled to a power supply voltage node in the package. The second end of the programmable element may be coupled to an external package connection (e.g., a package pin) and/or to an internal package node that connects to an input terminal of the integrated circuit die when the integrated circuit die is mounted in the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: A core voltage for a core logic region of an integrated circuit is specified by a programmable register on the integrated circuit. Output terminals on the integrated circuit are coupled to the programmable storage location and supply voltage control signals for a voltage regulator to specify the core voltage according to the contents of the programmable register. The output terminals may output a programmable voltage setting or a fixed voltage setting that specifies a default core voltage value, depending on reset conditions.

Abstract: A processor includes an input/output (I/O) register that is mapped into input/output (I/O) address space. The processor also includes a base address register that is loaded with a base address. The base address register may be a model specific register (MSR). The input/output register is accessed with an input/output instruction at an address determined according to the base address and an offset therefrom. The base address register may be accessible to software operating at a high privilege level and not accessible to software operating at a lower privilege level, while the I/O register is accessible to software operating at the lower privilege level. The processor determines when an I/O access is to the processor I/O register and accesses that I/O register without causing an input/output bus cycle that would otherwise occur.

Abstract: A memory controller generates speculative and non-speculative memory access requests. Several approaches are used to prevent speculative memory access requests from interfering with non-speculative memory access requests. When a request queue is full and contains at least one speculative request, that request is replaced in the memory access request queue with a non-speculative request. A counter associated with a speculative memory access request counts memory access requests. When a predetermined count value is reach, the speculative memory access request is assumed to be stale and retired from the request queue, thereby reducing possible interference by speculative accesses with non-speculative accesses and/or avoiding wasted bandwidth utilization by stale speculative access requests.

Abstract: A method and system for improving virtual memory performance, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. In the method and system, a request to access a first virtual memory address, correspondent to a first physical memory location resident within a first page of physical memory, is received. In response to the request to access the first virtual memory address, a Graphics Translation Look Aside Buffer entry is created. In response to a request to access a second virtual memory address, correspondent to a second physical memory address resident within a second physical memory area non-overlapping with the first physical memory page, the second physical memory location is accessed via the Graphics Translation Look Aside Buffer entry. The Graphics Translation Look Aside Buffer entry is constructed such that it translates a number of virtual memory addresses corresponding to a number of physical memory addresses.

Abstract: An improved sleep state provides the benefits of low latency wake up for normal situations, but also provides the ability to wake up in the event that system memory is corrupted during the sleep state due to, e.g., a power failure during that sleep state. Before entering the sleep state, the software operating on the computer system saves system state information relating to the computer system into system memory. In addition, the computer system saves that state information and an image of system memory to non-volatile memory such as a disk drive. At that point power is removed from most of the computer system but power is maintained to the system memory. In response to a wake-up event, the computer system determines if the contents of the system memory has been corrupted. If the contents of the system memory is valid, the state information in the system memory is used to restore the computer system.

Abstract: A memory controller detects an approaching end of a currently open page for an access operation for a particular data stream. The memory controller, in response to detecting the approaching end of the currently open page and if the particular data stream is of a predetermined type, such as an isochronous data stream, the memory controller speculatively opens a next page in the memory.