Patents by Inventor Qadeer Khan
Qadeer Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070018712Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.Type: ApplicationFiled: July 20, 2006Publication date: January 25, 2007Inventors: Siddhartha GK, Qadeer Khan, Divya Tripathi, Sanjay Wadhwa, Kulbhushan Misri
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Publication number: 20070018713Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.Type: ApplicationFiled: July 20, 2006Publication date: January 25, 2007Inventors: Divya Tripathi, Siddhartha Gk, Qadeer Khan, Kulbhushan Misri, Sanjay Wadhwa
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Publication number: 20060273425Abstract: A capacitor structure for an integrated circuit having at least first, second and third layers, with each layer having first and second conductors, includes multiple sidewall capacitors formed between sidewalls of the first conductor and the second conductor in each layer. Several inter-layer capacitors are formed between the first and second conductors in the first and second layers. Further, via capacitors are formed between sidewalls of adjacent vias corresponding to different conductors. The vias are formed between the second and third layers.Type: ApplicationFiled: April 13, 2006Publication date: December 7, 2006Inventors: Qadeer Khan, Kulbhushan Misri
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Publication number: 20060267671Abstract: A charge pump circuit for a high side drive circuit and a driver driving voltage circuit that stably output a voltage when input voltage is low. The charge pump circuit includes first and second transistors, first and second capacitors, and first to third diodes. The first capacitor has a high voltage side, connected to a load driving power supply voltage via the first diode, and a low voltage side, connected to the load driving power supply voltage via the first transistor or grounded via the second transistor driven in synchronization with the first transistor. The high voltage side is supplied, via the third diode, with a low side drive voltage that is as an output voltage of a low side charge pump, and functions to output high side drive voltage to a high side pre-driver circuit via the second diode.Type: ApplicationFiled: May 25, 2006Publication date: November 30, 2006Inventors: Qadeer Khan, Hidetaka Fukazawa, Tushar Nandurkar
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Publication number: 20060267641Abstract: A transmission line driver circuit that operates at a first voltage level is fabricated using devices that operate at a second, lower voltage level. The driver circuit includes a ramp generator that receives a speed signal and a data signal and generates a charge ramp signal and a discharge ramp signal. A pair of series connected source follower transistors have their gates connected to respective charge and discharge signal outputs of the ramp generator. The driver circuit output signal is generated at an output node between the sources of the NMOS and PMOS source follower transistors. A charge_ls generator circuit provides a charge_ls signal and a discharge_ls generator circuit provides a discharge_ls signal. A pair of protection transistors includes a first NMOS protection transistor and a first PMOS protection transistor, which are connected in series with respective ones of the source follower transistors, and their gates are connected to respective ones of the charge and discharge signals.Type: ApplicationFiled: May 30, 2006Publication date: November 30, 2006Inventors: Qadeer Khan, Divya Tripathi
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Patent number: 7132863Abstract: A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock signal period. The generator block is coupled to the input block. The generator block receives the pulse signal and divides a period of the pulse signal by a period of a high frequency digital signal and then generates an output clock signal with an output frequency that is about two times the input frequency.Type: GrantFiled: April 4, 2005Date of Patent: November 7, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Sanjay K. Wadhwa, Qadeer A. Khan, Kulbhushan Misri, Deeya Muhury
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Publication number: 20060220675Abstract: A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.Type: ApplicationFiled: April 4, 2005Publication date: October 5, 2006Inventors: Divya Tripathi, Qadeer Khan, Kulbhushan Misri
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Publication number: 20060220708Abstract: A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock signal period. The generator block is coupled to the input block. The generator block receives the pulse signal and divides a period of the pulse signal by a period of a high frequency digital signal and then generates an output clock signal with an output frequency that is about two times the input frequency.Type: ApplicationFiled: April 4, 2005Publication date: October 5, 2006Inventors: Sanjay Wadhwa, Qadeer Khan, Kulbhushan Misri, Deeya Muhury
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Patent number: 7102410Abstract: A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level uses only thin oxide transistors. The circuit includes a first unit operating at a first power supply voltage and receiving the input signal, a second unit operating at a second power supply voltage, and a third unit coupling the first unit to the second unit. The third unit enables generation of the output signal. Use of an extra fabrication mask for thick oxide transistors is avoided by using only thin oxide transistors.Type: GrantFiled: June 10, 2004Date of Patent: September 5, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Khan, Divya Tripathi, Kulbhushan Misri
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Patent number: 7084698Abstract: A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.Type: GrantFiled: October 14, 2004Date of Patent: August 1, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Khan, Sanjay K. Wadhwa, Kulbhushan Misri
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Patent number: 7061299Abstract: A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circuit operating at a high power supply voltage. The first circuit and the second circuit are connected to both of the I/O terminals. When a low voltage digital signal is applied at the first I/O terminal, a high voltage digital signal is generated at the second I/O terminal. Similarly, if a high voltage digital signal is applied at the second I/O terminal, a low voltage digital signal is generated at the first I/O terminal.Type: GrantFiled: August 8, 2005Date of Patent: June 13, 2006Assignee: Freescale Semiconductor, INCInventors: Qadeer A. Khan, Sanjay K. Wadhwa, Kulbhushan Misri
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Publication number: 20060082410Abstract: A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.Type: ApplicationFiled: October 14, 2004Publication date: April 20, 2006Inventors: Qadeer Khan, Sanjay Wadhwa, Kulbhushan Misri
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Publication number: 20060055570Abstract: A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circuit operating at a high power supply voltage. The first circuit and the second circuit are connected to both of the I/O terminals. When a low voltage digital signal is applied at the first I/O terminal, a high voltage digital signal is generated at the second I/O terminal. Similarly, if a high voltage digital signal is applied at the second I/O terminal, a low voltage digital signal is generated at the first I/O terminal.Type: ApplicationFiled: August 8, 2005Publication date: March 16, 2006Inventors: Qadeer Khan, Sanjay Wadhwa, Kulbhushan Misri
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Patent number: 7009424Abstract: A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup circuit such that when the level shifter is switched on, the first unit discharges an output node if the input signal is a logic low, and when the input signal is a logic high, the first unit charges a control node to the voltage of the input signal. The second unit is connected to the first unit and the high power supply voltage source, and also receives the input signal. The second unit shifts the input signal to the higher supply voltage output signal. The level shifter operates only at the high power supply voltage.Type: GrantFiled: June 10, 2004Date of Patent: March 7, 2006Assignee: Freescale Semiconductor, IncInventors: Qadeer A. Khan, Sanjay K. Wadhwa, Kulbhushan Misri
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Publication number: 20050275444Abstract: A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level uses only thin oxide transistors. The circuit includes a first unit operating at a first power supply voltage and receiving the input signal, a second unit operating at a second power supply voltage, and a third unit coupling the first unit to the second unit. The third unit enables generation of the output signal. Use of an extra fabrication mask for thick oxide transistors is avoided by using only thin oxide transistors.Type: ApplicationFiled: June 10, 2004Publication date: December 15, 2005Inventors: Qadeer Khan, Divya Tripathi, Kulbhushan Misri
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Publication number: 20050275429Abstract: A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup circuit such that when the level shifter is switched on, the first unit discharges an output node if the input signal is a logic low, and when the input signal is a logic high, the first unit charges a control node to the voltage of the input signal. The second unit is connected to the first unit and the high power supply voltage source, and also receives the input signal. The second unit shifts the input signal to the higher supply voltage output signal. The level shifter operates only at the high power supply voltage.Type: ApplicationFiled: June 10, 2004Publication date: December 15, 2005Inventors: Qadeer Khan, Sanjay Wadhwa, Kulbhushan Misri
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Publication number: 20050174158Abstract: A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circuit operating at a high power supply voltage. The first circuit and the second circuit are connected to both of the I/O terminals. When a low voltage digital signal is applied at the first I/O terminal, a high voltage digital signal is generated at the second I/O terminal. Similarly, if a high voltage digital signal is applied at the second I/O terminal, a low voltage digital signal is generated at the first I/O terminal.Type: ApplicationFiled: February 6, 2004Publication date: August 11, 2005Inventors: Qadeer Khan, Sanjay Wadhwa, Kulbhushan Misri