Patents by Inventor Qi-Ao Zhu
Qi-Ao Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954020Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.Type: GrantFiled: May 9, 2022Date of Patent: April 9, 2024Assignee: Hefei Core Storage Electronics LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Xu Hui Cheng
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Publication number: 20240028506Abstract: A mapping table re-building method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving write command from a host system, wherein the write command instructs storing first data to a first logical unit; performing a programming operation according to the write command to store the first data and identification information of the first logical unit to a first physical unit; updating a mapping table in response to the programming operation; detecting a table abnormal event related to the mapping table; reading the identification information of the first logical unit from the first physical unit in response to the table abnormal event; and re-building the mapping table according to the identification information of the first logical unit.Type: ApplicationFiled: August 8, 2022Publication date: January 25, 2024Applicant: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Yuting Niu, Yang Zhang
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Patent number: 11822798Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.Type: GrantFiled: December 19, 2021Date of Patent: November 21, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang
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Patent number: 11817172Abstract: A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.Type: GrantFiled: April 29, 2022Date of Patent: November 14, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Yang Zhang
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Publication number: 20230325310Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided.Type: ApplicationFiled: May 9, 2022Publication date: October 12, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Xu Hui Cheng
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Publication number: 20230326502Abstract: A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.Type: ApplicationFiled: April 29, 2022Publication date: October 12, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Yang Zhang
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Publication number: 20230297232Abstract: A table sorting method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to a first voltage management table among multiple voltage management tables; decoding the first data; in response to the first data being successfully decoded, updating count information corresponding to the first voltage management table; and in response to the count information meeting a default condition, increasing a usage priority of the first voltage management table among the voltage management tables.Type: ApplicationFiled: April 11, 2022Publication date: September 21, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Jian Hu
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Patent number: 11748026Abstract: A mapping information recording method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes multiple physical erasing units, and each of the physical erasing unit includes multiple physical programming units. The mapping information recording method includes: receiving first continuous data from a host system, wherein the host system instructs to store the first continuous data to a first continuous logical address; establishing a continuous mapping table to record a start logical address of the first continuous logical address, a length of the first continuous logical address, and a bitmap; writing the first continuous data into first physical programming units; and marking bits of virtual blocks corresponding to the first continuous logical address in the bitmap as a valid state, numbering the virtual blocks, and recording the numbers into the continuous mapping table.Type: GrantFiled: December 16, 2021Date of Patent: September 5, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang
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Patent number: 11693567Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.Type: GrantFiled: November 22, 2021Date of Patent: July 4, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao
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Publication number: 20230205451Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.Type: ApplicationFiled: January 19, 2022Publication date: June 29, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
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Patent number: 11669270Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.Type: GrantFiled: January 19, 2022Date of Patent: June 6, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
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Publication number: 20230132837Abstract: A mapping information recording method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes multiple physical erasing units, and each of the physical erasing unit includes multiple physical programming units. The mapping information recording method includes: receiving first continuous data from a host system, wherein the host system instructs to store the first continuous data to a first continuous logical address; establishing a continuous mapping table to record a start logical address of the first continuous logical address, a length of the first continuous logical address, and a bitmap; writing the first continuous data into first physical programming units; and marking bits of virtual blocks corresponding to the first continuous logical address in the bitmap as a valid state, numbering the virtual blocks, and recording the numbers into the continuous mapping table.Type: ApplicationFiled: December 16, 2021Publication date: May 4, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang
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Publication number: 20230127512Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.Type: ApplicationFiled: November 22, 2021Publication date: April 27, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao
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Publication number: 20230098366Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.Type: ApplicationFiled: October 13, 2021Publication date: March 30, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Wan-Jun Hong
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Patent number: 11281402Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.Type: GrantFiled: January 22, 2020Date of Patent: March 22, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Wan-Jun Hong, Ya-Lin Zhu, Tong-Jin Liu
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Patent number: 11221791Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.Type: GrantFiled: August 22, 2019Date of Patent: January 11, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Xin Wang, Kai-Di Zhu
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Patent number: 11175847Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: GrantFiled: March 18, 2020Date of Patent: November 16, 2021Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng
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Publication number: 20210223976Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: ApplicationFiled: March 18, 2020Publication date: July 22, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng
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Publication number: 20210181981Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.Type: ApplicationFiled: January 22, 2020Publication date: June 17, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Wan-Jun Hong, Ya-Lin Zhu, Tong-Jin Liu
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Patent number: 10922028Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes presetting a programming mode of a plurality of first type physical erasing units as a first programming mode, and presetting a programming mode of a plurality of second type physical erasing units as a second programming mode. The method also includes obtaining a change parameter according to usage parameters of the first type physical erasing units and the second type physical erasing units. The method further includes determining whether the change parameter matches a first change condition, and if the change parameter matches the first change condition, programming a write-data into the second type physical erasing unit by using the first programming mode.Type: GrantFiled: May 9, 2017Date of Patent: February 16, 2021Assignee: Hefei Core Storage Electronic LimitedInventors: Hao-Zhi Lee, Qi-Ao Zhu, Meng Xiao, Hui Xie