Abstract: Aspects of data modification for neural networks are described herein. The aspects may include a data modifier configured to receive input data and weight values of a neural network. The data modifier may include an input data configured to modify the received input data and a weight modifier configured to modify the received weight values. The aspects may further include a computing unit configured to calculate one or more groups of output data based on the modified input data and the modifier weight values.

Abstract: A unique novel reagent container device with a unique grid structure that allows for the sealing of liquids including volatile liquids. The reagent container device of the present disclosure comprises a container that can be sealed and a support system that forms a grid for sealing the top of the container. Such support system does not restrict liquid flow nor forms an additional section or well within the container device.

Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.

Abstract: The present disclosure provides a processing device and method. The device includes: an input/output module, a controller module, a computing module, and a storage module. The input/output module is configured to store and transmit input and output data; the controller module is configured to decode a computation instruction into a control signal to control other modules to perform operation; the computing module is configured to perform four arithmetic operation, logical operation, shift operation, and complement operation on data; and the storage module is configured to temporarily store instructions and data. The present disclosure can execute a composite scalar instruction accurately and efficiently.

Abstract: Aspects of a neural network operation device are described herein. The aspects may include a matrix element storage module configured to receive a first matrix that includes one or more first values, each of the first values being represented in a sequence that includes one or more bits. The matrix element storage module may be further configured to respectively store the one or more bits in one or more storage spaces in accordance with positions of the bits in the sequence. The aspects may further include a numeric operation module configured to calculate an intermediate result for each storage space based on one or more second values in a second matrix and an accumulation module configured to sum the intermediate results to generate an output value.

Abstract: In certain embodiments, the disclosure provides a method for increasing the efficiency of homology directed repair (HDR) in the genome of a cell, comprising: (a) introducing into the cell: (i) a nuclease; and (ii) a donor nucleic acid which comprises a modification sequence to be inserted into the genome; and (b) subjecting the cell to a temperature shift from 37° C. to a lower temperature; wherein the nuclease cleaves the genome at a cleavage site in the cell, and the donor nucleic acid directs the repair of the genome sequence with the modification sequence through an increased rate of HDR.

Abstract: A neural network processing method, comprising the following steps: obtaining a model dataset and model structure parameters of an original network (S100); obtaining an operational attribute of each compute node in the original network; operating the original network according to the model dataset and the model structure parameters of the original network and the operational attribute of each compute node, to obtain an instruction corresponding to each compute node in the original network (S200); and if the operational attribute of the current compute node is a first operational attribute, storing a network weight and the instruction corresponding to the current compute node into a first non-volatile memory, so as to obtain a first offline model corresponding to the original network (S300). Further provided are a computer system and a storage medium.

Abstract: An electronic apparatus performs a method of simulating visual effect of avalanche of media. The method includes: interpolating particle information of the media to a grid; simulating advection of fluid from the media; applying a computed drag force to the interpolated particle information on the grid and to the simulated advection of the fluid; interpolating updated particle information from the grid; simulating fluid projection from the media; determining whether a fluid generation condition is satisfied; in response to the determination that the fluid generation condition is satisfied: generating additional fluid from the media; and applying a fluid decaying scheme.

Abstract: A device includes a memory that stores a prefetching model. A control module receives a content page including one or more links each associated with selectable content and collects data associated with the content page. The collected data includes at least one of first data indicative of respective relationships between each of the links and a viewport of the device and second data indicative of characteristics of the viewport. The control module further assigns, using the prefetching model, respective scores to each of the links based on the collected data, and selectively generates, based on the assigned scores, a request to prefetch the selectable content associated with at least one of the links.

Abstract: Raycast-based calibration techniques are described for determining calibration parameters associated with components of a head mounted display (HMD) of an augmented reality (AR) system having one or more off-axis reflective combiners. In an example, a system comprises an image capture device and a processor executing a calibration engine. The calibration engine is configured to determine correspondences between target points and camera pixels based on images of the target acquired through an optical system, the optical system including optical surfaces and an optical combiner. Each optical surface is defined by a difference of optical index on opposing sides of the surface. At least one calibration parameter for the optical system is determined by mapping rays from each camera pixel to each target point via raytracing through the optical system, the raytracing being based on the index differences, shapes, and positions of the optical surfaces relative to the one or more cameras.

Abstract: Disclosed is a depth sensor for determining depth. The depth sensor can include a photosensor, a metalens configured to manipulate light to simultaneously produce at least two images having different focal distances on a surface of the photosensor, and processing circuitry configured to receive, from the photosensor, a measurement of the at least two images having different focal distances. The depth sensor can determine, according to the measurement, a depth associated with at least one feature in the at least two images.

Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.

Abstract: A chromosome segment derived from G. anomalum leading to a lethal phenotype in G. hirsutum, and molecular markers thereof are provided. The chromosome segment A11-9 is derived from G. anomalum, is located on chromosome 11 of a G. anomalum genome, and is marked by 6 pairs of simple sequence repeat (SSR) markers: NAU5192, A11_175, JAAS3191, A11_243, JAAS3310, and A11_1193. With DNA of G. anomalum as a template, the 6 pairs of SSR markers are used together to amplify the DNA of G. anomalum, and a chromosome segment with target fragments of the 6 pairs of SSR markers is the G. anomalum chromosome segment A11-9. A single chromosome segment introgression line derived from G. anomalum with a lethal phenotype is obtained, and the development of the single chromosome segment introgression line provides an important material for promoting the fine mapping of a target gene and the subsequent map-based cloning.

Abstract: A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.

Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.

Abstract: The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.

Abstract: A device includes a memory that stores a prefetching model. A control module receives a content page including one or more links each associated with selectable content and collects data associated with the content page. The collected data includes at least one of first data indicative of respective relationships between each of the links and a viewport of the device and second data indicative of characteristics of the viewport. The control module further assigns, using the prefetching model, respective scores to each of the links based on the collected data, and selectively generates, based on the assigned scores, a request to prefetch the selectable content associated with at least one of the links.

Abstract: Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.