Patents by Inventor Qi S. Wang

Qi S. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio
    Patent number: 11461504
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
  • APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AND VOLTAGES
    Publication number: 20210049307
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
  • Apparatus for autonomous security and functional safety of clock and voltages
    Patent number: 10824764
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
  • APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AND VOLTAGES
    Publication number: 20200004990
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh