Abstract: A lock, a vehicle parking system, and a vehicle parking method are provided. The lock includes a main body, a lock switch, a lock controller, a lock communication circuit, and a battery. The battery is connected to the lock switch, the lock controller, and the lock communication circuit, and configured to supply electrical energy to the lock switch, the lock controller, and the lock communication circuit. The lock communication circuit is connected to the lock controller, and transmits a locking instruction or an unlocking instruction to the lock controller when receiving the locking instruction or the unlocking instruction from a second device located outside the lock. The lock controller is connected to the lock switch connected to the main body, and the lock controller controls, when receiving the locking instruction or the unlocking instruction, the main body to perform a locking operation or an unlocking operation through the lock switch.

Abstract: A point-of-interest (POI) information management method includes: obtaining a webpage link; obtaining a webpage text associated with the webpage link; obtaining at least one item of POI information matching the webpage text from a POI information repository; presenting the at least one item of the POI information; in response to a pre-determined operation being performed on a first item of the POI information of the at least one item of the POI information, presenting a route from a current location to an address indicated in the first item of the POI information and a first operable icon; and in response to detecting another pre-determined operation is performed on the first operable icon, setting the route as a target trip.

Abstract: A network security management method is provided. In the method, configuration data that includes at least one access control policy for a network asset of a target cloud tenant is received. The network asset includes a private network, a subnet of the private network, and a cloud instance of the subnet. A network management and control unit and an access control policy set corresponding to the network management and control unit are determined according to the configuration data. The network management and control unit includes one or more of a private network-level management and control unit, a subnet-level management and control unit, and an instance-level management and control unit. The access control policy set of the network management and control unit is transmitted to the cloud instance that is associated with the network management and control unit to manage network traffic of the cloud instance.

Abstract: The present invention falls within the field of genetic engineering. More particularly, disclosed is a gene for expressing a fusion protein of human collagen and human fibronectin, which is expressed and purified in vitro by means of a genetic engineering method. By means of using Pichia pastoris as an expression host cell, a new-type, highly active recombinant fusion protein can be provided.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer located in the semiconductor substrate and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the resistive layer has a variable resistance; a first oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the first oxygen grasping layer is located above the resistive layer; a second oxygen grasping layer located in the bottom electrode metal layer, where upper surfaces of the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer are flush, and the resistive layer covers the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer.

Abstract: An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.

Abstract: In example implementations, an electronic device is provided. The electronic device includes a sensor, and a processor. The sensor is to detect a movement of a hand of a user controlling a virtual input device. The processor is communicatively coupled to the sensor. The processor is to translate the movement of the hand of the user detected by the sensor into a control input to the electronic device and to execute the control input.

Abstract: An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

Abstract: Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract: A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.