Abstract: A method, computer system, and a computer program product for data compression is provided. The present invention may include receiving operational data. The present invention may include profiling the operational data using one or more normalizing functions. The present invention may include extracting a plurality of patterns from the operational data. The present invention may include compressing the operational data based on the plurality of patterns extracted.

Abstract: Absorbent articles (30) have bonded materials and bond patterns. One of the absorbent articles (30) has a bond pattern (150a-150d) comprising bonds (151,153,155,155a-155d). The bond pattern (150a-150d) comprises a longitudinally extending series of bonds (151,153), which comprises a first bond (151) and a second bond (153) disposed longitudinally adjacent to the first bond (151). The first bond (151) has an inboard lateral edge (158), an outboard lateral edge (156), a top edge (152), and a bottom edge (154) having a recess portion (164). The second bond (153) has an inboard lateral edge (158) and an outboard lateral edge (156), a top edge (152) having a recess portion (164), and a bottom edge (154).

Abstract: A quantum layout optimization method includes: determining target Hamiltonian parameters of a quantum device; determining an initial quantum layout of the quantum device and initial geometric parameters of the initial quantum layout; determining a target gradient of Hamiltonian parameters of the quantum device to geometric parameters of the initial quantum layout; and adjusting the initial geometric parameters based on the target gradient to have the Hamiltonian parameters of the quantum device be the target Hamiltonian parameters to obtain a target quantum layout.

Abstract: A computer implemented method for debugging computer instructions is provided. The method comprises using a number processors to receive a computer program, including a source code and generate a number of information records associated with a number of computer instructions in the source code, wherein at least one of the computer instructions comprises a function enclosed by a macro. The processors create a data structure based on the information records and generate an index of identifiers in the data structure based on debug information of the computer instructions, wherein the index comprises respective identifying entries for the computer instructions. The processors update information records according to the identifying entries in the data structure.

Abstract: A dock assembly includes a docking station and a stand or mount coupled to the docking station. The dock assembly may be configured for an unmanned aerial vehicle (UAV). The docking station may include a landing surface configured to interface with the UAV, an extended portion coupled to the landing surface and extending from the landing surface, and a fiducial located on the extended portion.

Abstract: A battery configured to power an unmanned aerial vehicle. The battery includes an enclosure configured to house a power module of the battery. The battery also includes one or more conducting contacts located on the enclosure configured to contact one or more pogo pins of a battery charger located on a docking station of the unmanned aerial vehicle.

Abstract: The present invention provides a medical image segmentation method based on a Boosting-Unet segmentation network. By dividing training of an overall segmentation network into training of m sub segmentation networks, the method inherits convolution kernel parameters of the (k?1)th sub segmentation network during training of the kth sub segmentation network, thereby greatly decreasing the quantity of the convolution kernel parameters during every training and improving the learning ability of the network and the resistance to noise and image blur. In addition, a plurality of sub segmentation networks are arranged, so that the efficiency of the network is improved, a depth of an image data feature is also extracted, and the image data is segmented precisely, thereby improving the learning ability of the overall segmentation network to the image data feature, enhancing the robustness to noise disturbance information and further improving the performance of image segmentation.

Abstract: A method may include obtaining parameter information of a plurality of acquisition devices that communicate with the system to transmit video data to the system. The parameter information of each of the plurality of acquisition device may include transmission information of a target key frame of the video data of the acquisition device. The method may also include determining, based on the parameter information, whether there are collision key frames in the target key frames of the plurality of acquisition devices. The method may also include adjusting an original generation time of at least one of the collision key frames in response to determining that there are collision key frames, so that after the adjustment, there is no collision key frame in the target key frames of the plurality of acquisition devices.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining that a log multi-process debug mode is specified; obtaining a log file for debugging a source code, wherein the log file includes a plurality of log records; inserting a plurality of process identifier fields into each current log record in the log file; inserting a new log record into the log file for a created new process; and providing for performance of debugging for the source code based in part on the plurality of process identifier fields inserted into each current log record.

Abstract: Systems and methods to perform remote monitoring on a vehicle are described. One embodiment determines a state of a vehicle, where data associated with the vehicle is collected and logged. The data is transmitted to a data server. The data is processed, and vehicle information is extracted from the data. A state of the vehicle is determined based on the vehicle information.

Abstract: An unmanned aerial vehicle (UAV) is disclosed that includes a power source. The power source includes: one or more power cells; one or more thermal transfer members that are thermally connected to the one or more power cells; and a heat exchanger that is thermally connected to the one or more thermal transfer members such that the one or more thermal transfer members and the heat exchanger facilitate a transfer of thermal energy between the power source and ambient air to decrease or increase temperature of the power source.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining that a log multi-process debug mode is specified; obtaining a log file for debugging a source code, wherein the log file includes a plurality of log records; inserting a plurality of process identifier fields into each current log record in the log file; inserting a new log record into the log file for a created new process; and providing for performance of debugging for the source code based in part on the plurality of process identifier fields inserted into each current log record.

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.

Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

Abstract: In one embodiment of the present disclosure, an original graph including nodes is obtained. The nodes of the original graph are reordered to generate a reordered graph. Non-zero elements in an adjacency matrix for the reordered graph are clustered as compared with an adjacency matrix for the original graph. The adjacency matrix for the reordered graph is encoded with integers. The integers correspond to non-empty blocks in the adjacency matrix for the reordered graph.

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.