Abstract: A system including a reconfigurable processor, a runtime execution engine, a graph scheduler, and a communication scheduler is presented. The graph scheduler and the communication scheduler receive a dataflow graph and static schedules of graph and communication operations from a compiler. The graph scheduler and the communication scheduler generate new schedules of graph and communication operations based on user-defined schedules of graph and communication operations and the static schedules of graph and communication operations. The runtime execution engine uses the dataflow graph and the new schedules of graph and communication operations to configure an array of reconfigurable units in the reconfigurable processor for execution of the dataflow graph. The present technology also relates to a method of operating such a system, and to a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a system.

Abstract: A data processing system comprises a coarse-grained reconfigurable (CGR) processor including an array of reconfigurable units which are configured to execute a dataflow graph. The system further includes a compiler coupled to provide a configuration file including a configuration for a set of components in a plurality of components in the array of reconfigurable units. The configuration file is coupled to configure the set of components using the configuration. An intelligent redundancy management framework (IRMF) checks health of the configuration and identify the configuration as defective if a component in the set of component is defective. further performs a healing operation for the defective configuration by replacing the defective configuration with an alternate configuration using a different set of all healthy components.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A unified management framework for mediating access to an entity that interacts with a reconfigurable processor is presented. Furthermore, a system is presented that includes a reconfigurable processor configured to execute a dataflow graph, an entity that provisions and deprovisions the dataflow graph on the reconfigurable processor and that controls execution of the dataflow graph on the reconfigurable processor, and a unified management framework for mediating access to the entity and to the reconfigurable processor. Moreover, a method of operating a unified management framework for mediating access to an entity that interacts with a reconfigurable processor is presented.

Abstract: A polymer electrolyte can be formed from (e.g., by polymerizing) a mixture that includes oligomer(s), additive(s), solvent(s), salt(s), and/or any suitable components. The polymer electrolyte can further or alternatively include monomer(s) (e.g., a stiffening monomer that in solution or incorporated into a cured polymer modifies a mechanical property such as flexural modulus of the battery cell; adhesion monomers such as a monomer that interacts with one or more surface within a battery to modify or improve adhesion of the electrolyte and the surface; etc.).

Abstract: A data access method and apparatus for a heterogeneous processing system includes a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor maps virtual addresses of the second memory to physical addresses of the switch and bus circuitry. The first processor is configured to directly access the second memory using the mapped physical addresses, and may be configured to directly access the second memory for reading and writing data while executing an application.

Abstract: Disclosed herein are resin compositions comprising a (meth)acrylic polymer comprising at least one pendant silane functional group and a silane functional group equivalent weight of 500 g/eq to 9,000 g/eq. Also disclosed herein are coating compositions comprising any of the resin compositions disclosed herein and an accelerator. Also disclosed herein are coating compositions comprising a resin composition comprising a (meth)acrylic polymer comprising at least one pendant silane functional group; and an accelerator. Also disclosed are substrates comprising a coating formed on a surface from compositions disclosed herein. Also disclosed are uses of the compositions disclosed herein.

Abstract: A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.

Abstract: An embodiment of the present disclosure provides a dimming glass, including: a glass substrate; and at least two dye liquid crystal cells on the glass substrate. The dye liquid crystal cells are mutually stacked and bonded with each other via an adhesive layer. The dye liquid crystal cell includes a central region and a peripheral region surrounding a periphery of the central region. The dye liquid crystal cell includes a cell gap adjusting structure in at least the peripheral region, which is configured to adjust a cell gap of the dye liquid crystal cell to be consistent. An embodiment of the present disclosure further provides a transportation device, including the dimming glass described above and used as a window glass of the transportation device.

Abstract: A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

Abstract: A package coated on at least a portion thereof with a coating, the coating bring derived from a solvent-borne coating composition, the solvent-borne coating composition comprising: a) an acrylic material having one or more terminal and/or side group(s) of Formula (I) wherein X represents an organic bridging group comprising at least 5 (five) carbon atoms; and Y represents an oxygen (O), nitrogen (N) or sulphur(S) atom: b) a crosslinker material operable to crosslink the hydroxyl functionality on the acrylic material; and c) a carrier comprising a solvent.

Abstract: A speech brain-computer interface neural decoding system based on Chinese language, a method for controlling the speech brain-computer interface neural decoding system, and a method for implementing the speech brain-computer interface neural decoding system are disclosed. The speech brain-computer interface neural decoding system includes an electroencephalography (EEG) data acquisition module, a significance feature screening and verification module, a speech imagery EEG data decoding module, and an understandable speech synthesis module. The speech brain-computer interface neural decoding system integrates EEG data collection, EEG feature extraction, EEG feature screening, EEG signal decoding for reconstructing speech spectrum information and understandable speech synthesis. After obtaining reconstructed spectrogram features, a Pearson correlation analysis may be performed with original spectrogram features, with a correlation generally being ?80%.

Abstract: A heterogeneous processing system and method including a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to directly access the second memory using the mapped physical addresses according to memory extension operation. The first processor may be a reconfigurable processor, a reconfigurable dataflow unit, or a compute engine. The first processor may directly read data from or directly write data to the second memory while executing an application. The method may include configuring the first processor to directly access the second memory while executing an application for reading or writing data.

Abstract: A data processing system including an array of reconfigurable units and a compiler configured to generate to execute a dataflow graph of a user application is disclosed. The dataflow graph includes a sequence of temporal partitions, each temporal partition including a sequence of graph control operations. Also disclosed is an intelligent graph orchestration and execution engine (IGOEE) configured to receive an optimization objective from the complier. The optimization objective can be for minimizing execution time of the reconfigurable processor or maximizing computing resource utilization of the reconfigurable processor. The IGOEE can reorganize the sequence of temporal partitions and the sequence of graph control operations within each temporal partition to satisfy the optimization objective; and execute the reorganized dataflow graph on the reconfigurable processor. A corresponding method is also disclosed herein.

Abstract: A data processing system includes an array of reconfigurable units and a compiler configured to generate one or more configuration files for an application for execution on one or more reconfigurable processors. The data processing system further includes an execution flow logic which is configured to cause execution of the configuration files on the reconfigurable processors to be dependent upon one or more breakpoint conditions. The data processing further includes a runtime logic configured to execute the configuration files depending upon the breakpoint conditions. A corresponding method is also disclosed herein.

Abstract: A two-component waterborne coating system includes: a first component including an acid-functional polymer having an acid value of at least 100, based on total resin solids, dispersed in an aqueous medium; and a second component separate from the first component. The second component includes an epoxy-functional compound. A method of preparing a two-component waterborne coating system and two-component waterborne coating system kit are also described herein.

Abstract: Provided are a method and apparatus for blockchain community governance, a device and a storage medium. The method is described below. A community governance transaction request initiated by a blockchain account and a governance scene to which the community governance transaction request belongs are acquired. Community governance authority of the blockchain account in the governance scene is verified according to the governance scene and governance token resource information in the blockchain account. In a case where a community governance authority verification is successful, the community governance transaction request is executed.

Abstract: An embodiment of the present disclosure provides a dimming glass, including: a glass substrate; and at least two dye liquid crystal cells on the glass substrate. The dye liquid crystal cells are mutually stacked and bonded with each other via an adhesive layer. The dye liquid crystal cell includes a central region and a peripheral region surrounding a periphery of the central region. The dye liquid crystal cell includes a cell gap adjusting structure in at least the peripheral region, which is configured to adjust a cell gap of the dye liquid crystal cell to be consistent. An embodiment of the present disclosure further provides a transportation device, including the dimming glass described above and used as a window glass of the transportation device.

Abstract: A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.