Patents by Inventor Qi Zuo
Qi Zuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10229072Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.Type: GrantFiled: March 31, 2014Date of Patent: March 12, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Ku Hong Jeong, Qi Zuo, Shaohua Yang, Kaitlyn T. Nguyen
-
Patent number: 9804919Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.Type: GrantFiled: July 20, 2015Date of Patent: October 31, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Yuqing Yang, Shaohua Yang, Xuebin Wu, Qi Zuo
-
Publication number: 20170024274Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.Type: ApplicationFiled: July 20, 2015Publication date: January 26, 2017Inventors: Yuqing Yang, Shaohua Yang, Xuebin Wu, Qi Zuo
-
Patent number: 9542982Abstract: An apparatus for processing data includes a data processing circuit configured to process user data, wherein the data processing circuit comprises a number of sub-circuits, a number of clock gates each configured to control a clock signal to one of the sub-circuits, a gating control circuit configured to control the clock gates to apply the clock signal to each of the sub-circuits in staged fashion during a ramped power up operation, and a dummy data source configured to provide dummy data to the data processing circuit during the ramped power up operation of the data processing circuit.Type: GrantFiled: December 10, 2015Date of Patent: January 10, 2017Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Kaitlyn T. Nguyen, Shaohua Yang, Dan Liu, Xiao Dong Yan, Qi Zuo
-
Publication number: 20160277035Abstract: A non-binary low density parity check decoder includes a check node processor configured to generate check node to variable node messages based on variable node to check node messages, and a variable node processor configured to generate the variable node to check node messages and to calculate perceived values of variable nodes based on the check node to variable node messages. The variable node to check node messages and the check node to variable node messages are in a normalized format. The variable node processor includes an adder configured to add likelihood values in a non-normalized format, wherein only one of two inputs to the adder are converted from the normalized format to the non-normalized format in a zero-padding circuit.Type: ApplicationFiled: March 18, 2015Publication date: September 22, 2016Inventors: Dan Liu, Qi Zuo, Lei Wang, Shaohua Yang
-
Publication number: 20160191079Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a saturation circuit operable to reduce a precision in the variable node to check node messages, and a check node processor operable to generate the check node to variable node messages based on the variable node to check node messages at least in part by finding a minimum value, an index of the minimum value and a next minimum value of Q values in the variable node to check node messages. The check node processor includes a switching circuit operable to update the minimum and the next minimum values and is operable to disable the switching circuit based at least in part on a comparison between the Q values and the next minimum value.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Qi Zuo, Shu Li, Dan Liu
-
Patent number: 9304910Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.Type: GrantFiled: January 13, 2014Date of Patent: April 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Qi Zuo, Kuhong Jeong, Shu Li, Xiang Wang, Han Fang, Shaohua Yang
-
Publication number: 20160091951Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for scheduling in a data decoder.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Yang Han, Qi Zuo, Dan Liu, Shaohua Yang
-
Publication number: 20160020783Abstract: An apparatus for low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to update variable node values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages based on the variable node to check node messages. The variable node processor and the check node processor comprise a quasi-cyclic decoder with relative indexes that refer to non-zero circulants.Type: ApplicationFiled: July 17, 2014Publication date: January 21, 2016Inventors: Shaohua Yang, Shu Li, Dan Liu, Qi Zuo
-
Patent number: 9190104Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.Type: GrantFiled: March 13, 2013Date of Patent: November 17, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Shaohua Yang, Kapil Gaba, Yoon L. Liow, Xuebin Wu, Qi Zuo, YuQing Yang, Lei Wang
-
Publication number: 20150269097Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.Type: ApplicationFiled: March 31, 2014Publication date: September 24, 2015Applicant: LSI CorporationInventors: Ku Hong Jeong, Qi Zuo, Shaohua Yang, Kaitlyn T. Nguyen
-
Patent number: 9130590Abstract: A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.Type: GrantFiled: November 3, 2013Date of Patent: September 8, 2015Assignee: LSI CORPORATIONInventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang
-
Publication number: 20150161045Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.Type: ApplicationFiled: January 13, 2014Publication date: June 11, 2015Applicant: LSI CorporationInventors: Qi Zuo, Kuhong Jeong, Shu Li, Xiang Wang, Han Fang, Shaohua Yang
-
Patent number: 9048867Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.Type: GrantFiled: May 21, 2013Date of Patent: June 2, 2015Assignee: LSI CorporationInventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang
-
Patent number: 9015550Abstract: The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.Type: GrantFiled: October 5, 2012Date of Patent: April 21, 2015Assignee: LSI CorporationInventors: Chung-Li Wang, Dan Liu, Qi Zuo, Zongwang Li, Shaohua Yang
-
Publication number: 20150092290Abstract: A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.Type: ApplicationFiled: November 3, 2013Publication date: April 2, 2015Applicant: LSI CorporationInventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang
-
Publication number: 20140351671Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.Type: ApplicationFiled: May 21, 2013Publication date: November 27, 2014Applicant: LSI CorporationInventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang
-
Patent number: 8773799Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.Type: GrantFiled: December 21, 2012Date of Patent: July 8, 2014Assignee: LSI CorporationInventors: Suharli Tedja, Shaohua Yang, Fan Zhang, Qi Zuo, Joseph Garofalo, Yu Kou
-
Publication number: 20140181570Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: LSI CorporationInventors: Suharli Tedja, Shaohua Yang, Fan Zhang, Qi Zuo, Joseph Garofalo, Yu Kou
-
Publication number: 20140172934Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing.Type: ApplicationFiled: March 13, 2013Publication date: June 19, 2014Applicant: LSI CorporationInventors: Shaohua Yang, Kapil Gaba, Yoon L. Liow, Xuebin Wu, Qi Zuo, YuQing Yang, Lei Wang