Patents by Inventor Qian Fu
Qian Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128091Abstract: A method includes providing, within an etch chamber, a base structure including a target layer disposed on a substrate, and an etch mask disposed on the target layer, dry etching, within the etch chamber, the target layer using thionyl chloride to obtain a processed base structure, and after forming the plurality of features. The processed base structure includes a plurality of features and a plurality of openings defined by the etch mask. The method further includes removing the processed base structure from the etch chamber. In some embodiments, the target layer includes carbon. In some embodiments, the dry etching is performed at a sub-zero degree temperature.Type: ApplicationFiled: July 12, 2023Publication date: April 18, 2024Inventors: Zhonghua Yao, Qian Fu, Mark J. Saly, Yang Yang, Jeffrey W. Anthis, David Knapp, Rajesh Sathiyanarayanan
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Patent number: 11944264Abstract: The present invention relates to the technical field of endoscopes, and discloses a confocal endoscope with a fixing device.Type: GrantFiled: June 22, 2021Date of Patent: April 2, 2024Assignee: HAINAN UNIVERSITYInventors: Qian Liu, Ling Fu, Xiaoxiao Ma, Gang Zheng, Yu Feng
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Patent number: 11935751Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.Type: GrantFiled: May 25, 2021Date of Patent: March 19, 2024Assignee: Applied Materials, Inc.Inventors: Siyu Zhu, Chuanxi Yang, Hang Yu, Deenesh Padhi, Yeonju Kwak, Jeong Hwan Kim, Qian Fu, Xiawan Yang
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Patent number: 11913184Abstract: A snow thrower includes a motor, an auger driven by the motor to rotate, a handle device for a user to operate, an auger housing for containing the auger and a frame for connecting the handle device and the auger housing. The auger housing is made of at least two different materials.Type: GrantFiled: April 27, 2021Date of Patent: February 27, 2024Assignee: Chervon (HK) LimitedInventors: Xiangqing Fu, Feng Yuan, Keqiong Zhong, Qian Liu, Li Li, Toshinari Yamaoka, Fangjie Nie, Liang Chen
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Publication number: 20240038833Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.Type: ApplicationFiled: July 14, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Fredrick Fishburn, Tomohiko Kitajima, Qian Fu, Srinivas Guggilla, Hang Yu, Jun Feng, Shih Chung Chen, Lakmal C. Kalutarage, Jayden Potter, Karthik Janakiraman, Deenesh Padhi, Yifeng Zhou, Yufeng Jiang, Sung-Kwan Kang
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Publication number: 20240030000Abstract: Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Inventors: Maolin Long, Zhongkui Tan, Ying Wu, Qian Fu, Alex Paterson, John Drewery
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Publication number: 20240014039Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a carbon-containing material. The boron-and-nitrogen-containing material comprises a plurality of openings. The methods may include etching the carbon-containing material.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Applicant: Applied Materials, Inc.Inventors: Jeong Hwan Kim, Yeonju Kwak, Qian Fu, Siyu Zhu, Chuanxi Yang, Hang Yu
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Publication number: 20230360920Abstract: Described herein is a method for etching a sample. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow comprising silicon tetrachloride (SiCl4) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Yifeng Zhou, Qian Fu
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Patent number: 11798785Abstract: Systems and methods for reverse pulsing are described. One of the systems includes a controller, first and second source radio frequency (RF) generators, and first and second bias RF generators. The controller controls the first source RF generator to generate a first source pulsed signal, and controls the second source RF generator to generate a second source pulsed signal. The system includes a first match circuit that receives the first and second source pulsed signals and combines the first and second source pulsed signals. The controller controls the first bias RF generator to generate a first bias pulsed signal, and controls the second bias RF generator to generate a second bias pulsed signal. The system includes a second match circuit that receives the first and second bias pulsed signals and combines the first and second bias pulsed signals into a combined bias signal.Type: GrantFiled: September 11, 2017Date of Patent: October 24, 2023Assignee: Lam Research CorporationInventors: Maolin Long, Zhongkui Tan, Ying Wu, Qian Fu, Alex Paterson, John Drewery
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Publication number: 20230245895Abstract: Exemplary semiconductor processing methods may include depositing a boron-containing material on the substrate. The boron-containing material may extend along sidewalls of the one or more features in the substrate. The methods may include forming a plasma of an oxygen-containing precursor and contacting the substrate with plasma effluents of the oxygen-containing precursor. The contacting may etch a portion of the one or more features in the substrate. The contacting may oxidize the boron-containing material.Type: ApplicationFiled: February 1, 2022Publication date: August 3, 2023Applicant: Applied Materials, Inc.Inventors: Zhonghua Yao, Qian Fu, Aaron Eppler, Mukund Srinivasan
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Patent number: 11646207Abstract: A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.Type: GrantFiled: November 29, 2018Date of Patent: May 9, 2023Assignee: Lam Research CorporationInventors: Ce Qin, Zhongkui Tan, Qian Fu, Sam Do Lee
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Publication number: 20230129550Abstract: Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may define one or more recessed features. The methods may include providing a second precursor to the processing region. The methods may include forming a plasma of the carbon-containing precursor and the second precursor in the processing region. Forming the plasma of the carbon-containing precursor and the second precursor may be performed at a plasma power of greater than or about 500 W. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more recessed features. The methods may include, subsequent depositing the carbon-containing material for a first period of time, applying a bias power while depositing the carbon-containing material for a second period of time.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu
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Publication number: 20230110474Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of less than or about 1,000 W. The methods may include depositing a silicon-containing material on the one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features at a rate of at least 2:1 relative to deposition on the exposed regions of the substrate.Type: ApplicationFiled: October 13, 2021Publication date: April 13, 2023Applicant: Applied Materials, Inc.Inventors: Yifeng Zhou, Qian Fu
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Publication number: 20220415648Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
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Publication number: 20220384189Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.Type: ApplicationFiled: May 25, 2021Publication date: December 1, 2022Applicant: Applied Materials, Inc.Inventors: Siyu Zhu, Chuanxi Yang, Hang Yu, Deenesh Padhi, Yeonju Kwak, Jeong Hwan Kim, Qian Fu, Xiawan Yang
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Publication number: 20220319601Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.Type: ApplicationFiled: March 28, 2022Publication date: October 6, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Qian Fu, Sung-Kwan Kang, Takehito Koshizawa, Fredrick Fishburn
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Publication number: 20210407811Abstract: A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.Type: ApplicationFiled: November 29, 2018Publication date: December 30, 2021Inventors: Ce QIN, Zhongkui TAN, Qian FU, Sam Do LEE
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Patent number: 11049726Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.Type: GrantFiled: November 20, 2017Date of Patent: June 29, 2021Assignee: Lam Research CorporationInventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, John Drewery
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Publication number: 20210193474Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, John Drewery
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Patent number: 10943789Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.Type: GrantFiled: November 21, 2017Date of Patent: March 9, 2021Assignee: Lam Research CorporationInventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, John Drewery