Abstract: Convolutional neural network-based image processing method and device are provided. The device includes a first on-chip memory and an arithmetic circuit configured to read a 3D feature map from a first on-chip memory by blocks the 3D feature map being divided into L blocks, perform processing of the current layer of the convolutional neural network on the 3D feature map by blocks; and store an output result of the current layer to the first on-chip memory. The first on-chip memory includes: S first storage spaces, each being used to store one of the L blocks included in the 3D feature map as input data of the current layer; and R second storage spaces, each being used to store output data of the current layer of one of the L blocks. L, S and R are integers greater than 1, and S and R are less than L.

Abstract: A data processing method and a processing circuit are provided. The method includes obtaining a first input data and a data length of the first input data; obtaining a first value according to a byte offset and the data length of the first input data, the first value including N bits, each bit of the first value is either a first identifier or a second identifier, and each bit corresponding to one storage queue; obtaining a second input data according to the byte offset and the first input data, each sub-data corresponding to one bit in the first value; selecting the sub-data corresponding to a bit having the first identifier, and storing the selected sub-data in the storage queue corresponding to the bit having the first identifier; and when a data output condition is satisfied, outputting the sub-data stored in the storage queue.

Abstract: A pooling device includes one or more first processing circuits and one or more second processing circuits. The one or more first processing circuits are configured to compute temporary pooling results of an input image along a row direction or a column direction. The one or more second processing circuits are configured to generate an output image according to the temporary pooling results of the input image along the row direction or the column direction.

Abstract: A neural network acceleration device includes a processor and a storage medium. The storage medium stores instructions that, when executed by the processor, cause the processor to obtain an input feature value, perform computation processing on the input feature value to obtain an output feature value, and in response to a fixed-point format of the output feature value being different from a predetermined fixed-point format, perform at least one of a low bit shifting operation or a high bit truncation operation on the output feature value according to the predetermined fixed-point format to obtain a target output feature value. A fixed-point format of the target output feature value is the predetermined fixed-point format.

Abstract: An arithmetic device for a neural network includes a controller and multiply-accumulate unit groups. A multiply-accumulate unit group includes a filter register and a plurality of computing units, and the filter register is connected to the plurality of computing units. The controller is configured to generate control information and transmit the control information to the plurality of computing units. The filter register is configured to cache filter weighted values of multiply-accumulate operations to be performed. The plurality of computing units is configured to cache input feature values of the multiply-accumulate operations to be performed and perform the multiply-accumulate operations on the filter weighted values and the input feature values according to received control information.

Abstract: The present disclosure relates to a computation apparatus for a neural network. The computation apparatus includes a first processing unit and a second processing unit. The first processing unit is configured to perform a first computation on k1 number of input feature data according to a size of a computation window to obtain an intermediate result, where a size of the computation window is k1×k2, and k1 and k2 are positive integers. The second processing unit is configured to perform a second computation on k2 number of intermediate results output by the first processing unit according to the size of the computation window to obtain a computation result.

Abstract: Nanowires are disclosed which comprise transition metal oxides. The transition metal oxides may include oxides of group II, group III, group IV and lanthanide metals. Also disclosed are methods for making nanowires which comprise injecting decomposition agents into a solution comprising solvents and metallic alkoxide or metallic salt precursors.

Abstract: Nanowires are disclosed which comprise transition metal oxides. The transition metal oxides may include oxides of group II, group III, group IV and lanthanide metals. Also disclosed are methods for making nanowires which comprise injecting decomposition agents into a solution comprising solvents and metallic alkoxide or metallic salt precursors.

Abstract: The present invention is to provide a method of downloading data from a PC to a PHS or vice versa, which comprises the steps of commanding a PC to edit data (e.g., phonebook, picture, or ring data) by a PHS, sending the edited data complying with the data requirements of the PHS to a data packet sending mechanism of the PC, and dividing the data into a plurality of data packets, sequentially sending the data packets to the PHS via a transfer interface of the PC, assembling the data packets for verification and storing the data packets in a corresponding area of the PHS.