Patents by Inventor Qian Tao
Qian Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968832Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.Type: GrantFiled: October 16, 2020Date of Patent: April 23, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
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Patent number: 11943928Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: GrantFiled: April 19, 2022Date of Patent: March 26, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
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Publication number: 20240083832Abstract: A method for preparing acetic acid by catalyst including the following steps is provided, S1. preparing the hydrotalcite carrier by hydrothermal method; S2. ion exchange; S3. liquid phase reduction; S4. placing the CoPd/LDH catalyst obtained in S3 in a two-channel fixed bed step-by-step continuous reactor, carrying out the reaction at 100-400° C. and 0.1-20 MPa, synthesizing acetic acid by alternating feeding of CH4+H2+H2O and CO2+H2+H2O, with the alternating time of 50-300 s. The present invention replaces the traditional process of acetic acid production including the steps of methane and carbon dioxide reforming to produce syngas. The process flow is short, the reaction conditions are mild, and the energy consumption and cost are greatly reduced.Type: ApplicationFiled: July 21, 2023Publication date: March 14, 2024Applicant: Taiyuan University of TechnologyInventors: Wei HUANG, Shiqi TAO, Yongjun LIU, Qian ZHANG, Ruijia WAMG, Yin TANG
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Patent number: 11889686Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.Type: GrantFiled: September 7, 2021Date of Patent: January 30, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao Shen, Li Hong Xiao, Yushi Hu, Qian Tao, Mei Lan Guo, Yong Zhang, Jian Hua Sun
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Publication number: 20230422504Abstract: A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Patent number: 11805643Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.Type: GrantFiled: August 31, 2021Date of Patent: October 31, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Ruo Fang Zhang, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Qian Tao
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Patent number: 11805646Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: November 24, 2020Date of Patent: October 31, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Patent number: 11746383Abstract: The present invention provides a method for diagnosing and determining prognosis of certain cancers (e.g., esophageal squamous cell carcinoma or ESCC) in a subject by detecting suppressed expression of the DLEC1 gene, which in some cases is due to elevated methylation level in the genomic sequence of this gene. A kit and device useful for such a method are also provided. In addition, the present invention provides a method for treating cancer by increasing DLEC1 gene expression or activity.Type: GrantFiled: August 2, 2019Date of Patent: September 5, 2023Assignee: The Chinese University of Hong KongInventors: Qian Tao, Lili Li
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Patent number: 11706929Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: GrantFiled: December 23, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
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Patent number: 11699657Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: GrantFiled: June 7, 2021Date of Patent: July 11, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Patent number: 11672191Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: GrantFiled: January 29, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun J. Hu, Everett A. McTeer
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Publication number: 20230084008Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20230083030Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: November 10, 2022Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 11502094Abstract: A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.Type: GrantFiled: March 28, 2019Date of Patent: November 15, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ruo Fang Zhang, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Qian Tao
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Patent number: 11462474Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: April 17, 2019Date of Patent: October 4, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20220238556Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: ApplicationFiled: April 19, 2022Publication date: July 28, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
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Patent number: 11380701Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 17, 2020Date of Patent: July 5, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Publication number: 20220208767Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.Type: ApplicationFiled: March 17, 2022Publication date: June 30, 2022Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
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Patent number: 11329061Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.Type: GrantFiled: September 10, 2018Date of Patent: May 10, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Qian Tao, Yushi Hu, Xiao Tian Cheng, Jian Xu, Haohao Yang, Yue Qiang Pu, Jin Wen Dong
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Publication number: 20220122998Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: ApplicationFiled: December 23, 2021Publication date: April 21, 2022Applicant: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan