Patents by Inventor Qian Tao

Qian Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238556
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11397737
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining cluster data, determining a portion of the search queries within the given query cluster that trigger a local search feature, assigning to the intent flag a value indicating that the given cluster is high local intent cluster when the portion of the search queries within the given query cluster that trigger the local search feature meets the local intent threshold, assigning to the intent flag a value indicating that the given cluster is a low local intent cluster when the portion of the search queries within the given query cluster that trigger the local search feature fails to meet the local intent threshold, and modifying a content item including adding a local content feature to the content item when the search query is determined to be included in the high local intent cluster.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 26, 2022
    Assignee: Google LLC
    Inventors: Qian Zhong, Claire McLeod, Yebin Tao
  • Publication number: 20220221270
    Abstract: A calibration method for fringe projection systems based on plane mirrors. Firstly, two mirrors are placed behind the tested object. Through the reflection of mirrors, the camera can image the measured object from the front and other two perspectives, so as to obtain 360-degree two-dimensional information of the measured object. The projector projects three sets of phase-shifting fringe patterns with frequencies of 1, 8, and 64. The camera captures the fringe image to obtain an absolute phase map with a frequency of 64 by using the phase-shifting method and the temporal phase unwrapping algorithm. By using the calibration parameters between the projector and the camera, the absolute phase map can be converted into three-dimensional information of the measured object. Then, the mirror calibration is realized by capturing a set of 3D feature point pairs, so that the 3D information from different perspectives is transformed into a unified world coordinate system.
    Type: Application
    Filed: August 7, 2020
    Publication date: July 14, 2022
    Applicant: Nanjing University of Science and Technology
    Inventors: Chao Zuo, Wei Yin, Qian Chen, Shijie Feng, Jiasong Sun, Tianyang Tao, Yan Hu, Liang Zhang, Jiaming Qian
  • Patent number: 11380701
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 5, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Publication number: 20220208767
    Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
  • Patent number: 11329061
    Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 10, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Qian Tao, Yushi Hu, Xiao Tian Cheng, Jian Xu, Haohao Yang, Yue Qiang Pu, Jin Wen Dong
  • Publication number: 20220122998
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
  • Patent number: 11309327
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11289487
    Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
  • Patent number: 11271004
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 8, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Patent number: 11264397
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11244951
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
  • Publication number: 20210408026
    Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 30, 2021
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Miao SHEN, Li Hong XIAO, Yushi HU, Qian TAO, Mei Lan GUO, Yong ZHANG, Jian Hua SUN
  • Patent number: 11211397
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11211393
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Patent number: 11207340
    Abstract: The present invention provides a method for assessing the risk of cancer in a subject by detecting elevated methylation level in the genomic sequence of the TET1 gene, which leads to suppressed expression of this gene. A kit and device useful for practicing such a method are also provided.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 28, 2021
    Assignee: The Chinese University of Hong Kong
    Inventors: Qian Tao, Lili Li
  • Publication number: 20210399001
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
  • Publication number: 20210398999
    Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ruo Fang ZHANG, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Qian Tao
  • Patent number: 11182406
    Abstract: A data-replication system replicates a source database to a target database by first intelligently identifying and prioritizing a set of hot queries that have each in the past been submitted to the source database at a rate exceeding a threshold submission rate. Any previously replicated content contained in a database table accessed by a hot query is copied to a set of memory-resident blocks. The blocks are then updated with incremental changes made to the table's contents since the most-recent previous replication. Each updated block is copied to the target database in order of the priority of the block's corresponding hot query. When all blocks that contain data of a particular table have been copied into the target database, that table becomes available to users of the target database despite the fact that the entire database has not yet been fully replicated.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: He Fang Zhang, Peng Hui Jiang, Wei Guo, Yue Li, Jin Ping Lin, Meng Zhao, Qian Tao
  • Patent number: 11145666
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang