Patents by Inventor Qian Tao

Qian Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098175
    Abstract: An electronic device comprises ferroelectric random access memory cells. One or more of the ferroelectric random access memory cells comprises a crystallized ferroelectric material and an electrode adjacent to the crystallized ferroelectric material. The crystallized ferroelectric material exhibits a dominant crystallographic orientation. The electrode comprises a crystalline material exhibiting an additional dominant crystallographic orientation inducing the dominant crystallographic orientation of the crystallized ferroelectric material. A memory device is also disclosed comprising an array of ferroelectric memory cells. The ferroelectric memory cell comprises a crystallized ferroelectric material having a first side and a second side opposite the first side, and an electrode adjacent the first side of the ferroelectric material. The crystallized ferroelectric material comprises a crystallized hafnium-based material exhibiting a dominant (200) crystallographic orientation.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 20, 2025
    Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
  • Publication number: 20250097588
    Abstract: Provided in the embodiments of the present application are a brightness measurement method and apparatus, a control method and apparatus for a photographic apparatus, and a medium. In the brightness measurement method, a brightness measurement circuit is used to perform brightness measurement, the brightness measurement circuit comprising: a photosensitive diode, a switch and at least two measurement groups.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 20, 2025
    Applicant: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guo AI, Qian TAO, Zuoxing YANG
  • Publication number: 20250031366
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Application
    Filed: October 4, 2024
    Publication date: January 23, 2025
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu LU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Qian TAO, Yu Ru HUANG, Si Ping HU, Lan YAO, Li Hong XIAO, A Man ZHENG, Kun BAO, Haohao YANG
  • Patent number: 12167610
    Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: December 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
  • Publication number: 20240367438
    Abstract: In some examples, the disclosure describes device that includes a moveable carriage, a supply manifold releasably coupled to the moveable carriage utilizing a locking mechanism, and a trigger arm coupled to the supply manifold to move the supply manifold a distance away from the moveable carriage while the locking mechanism is in an unlocked position.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 7, 2024
    Inventors: Deyang Wang, Adnil San Dela Pena Sazon, Qian Tao
  • Patent number: 12137558
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: November 5, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Publication number: 20240292622
    Abstract: A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 29, 2024
    Inventors: Zhenyu LU, Yu Ru HUANG, Qian TAO, Yushi HU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Yongna LI, Lidong SONG
  • Patent number: 12063780
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 13, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
  • Publication number: 20240241088
    Abstract: The present invention discloses a gas chromatography (GC) system for separating analytes from a matrix, comprising: a GC system entrance; a first column fluidically connected to the GC system entrance through a first valve; a second column fluidically connected to the first column through a second valve; a third column fluidically connected to the first column through the second valve; a fourth column fluidically connected to a third column through a third valve; and a GC system exit fluidically connected to both the fourth column and the second column through a fourth valve. And the present invention also discloses a method of separating various analytes, including analyte portions comprising one or more of Ar, O2, N2, CH4 and CO2, from a gas matrix and from CO2 by using the GC system.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 18, 2024
    Inventors: Ming-Hao HE, Wan LI, Li XU, Ting-Ting BU, Qian TAO
  • Patent number: 12010838
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 11, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Publication number: 20240179911
    Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Jun LIU, Zongliang HUO, Li Hong XIAO, Zhenyu LU, Qian TAO, Yushi HU, Sizhe LI, Zhao Hui TANG, Yu Ting ZHOU, Zhaosong LI
  • Patent number: 11991880
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 21, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
  • Patent number: 11968832
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 23, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
  • Patent number: 11943928
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11889686
    Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 30, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Miao Shen, Li Hong Xiao, Yushi Hu, Qian Tao, Mei Lan Guo, Yong Zhang, Jian Hua Sun
  • Publication number: 20230422504
    Abstract: A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11805646
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: October 31, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11805643
    Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 31, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ruo Fang Zhang, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Qian Tao
  • Patent number: 11746383
    Abstract: The present invention provides a method for diagnosing and determining prognosis of certain cancers (e.g., esophageal squamous cell carcinoma or ESCC) in a subject by detecting suppressed expression of the DLEC1 gene, which in some cases is due to elevated methylation level in the genomic sequence of this gene. A kit and device useful for such a method are also provided. In addition, the present invention provides a method for treating cancer by increasing DLEC1 gene expression or activity.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 5, 2023
    Assignee: The Chinese University of Hong Kong
    Inventors: Qian Tao, Lili Li
  • Patent number: 11706929
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan