Patents by Inventor Qian Tao
Qian Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190005996Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Christopher J. Larsen, David A. Daycock, Qian Tao, Saniya Rathod, Devesh K. Datta, Srivardhan Gowda, Rithu K. Bhonsle
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Publication number: 20180350824Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D.V. Nirmal Ramaswamy
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Patent number: 10147732Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: GrantFiled: March 23, 2018Date of Patent: December 4, 2018Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20180323212Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Applicant: Micron Technology, Inc.Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
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Patent number: 10083981Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.Type: GrantFiled: February 1, 2017Date of Patent: September 25, 2018Assignee: Micron Technology, Inc.Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
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Publication number: 20180270377Abstract: Examples of an imaging device (100) are described herein. In an example, the imaging device (100) includes a drive control assembly (110), a first drive assembly (106), a second drive assembly (108), a movable carriage (102), and a locking mechanism (112). The drive control assembly (110) can be used to regulate transmission of drive from an actuator (200) to the first drive assembly (106) and the second drive assembly (108). The locking mechanism (112) can lock the drive control assembly (110) in an engaged position with the first drive assembly (106) or the second drive assembly (108). The movable carriage (102) can actuate the locking mechanism (112) to lock the drive control assembly (110) in the engaged position.Type: ApplicationFiled: January 25, 2016Publication date: September 20, 2018Inventor: Qian Tao
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Patent number: 10062703Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: March 15, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
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Publication number: 20180219021Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.Type: ApplicationFiled: February 1, 2017Publication date: August 2, 2018Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
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Publication number: 20180145084Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: ApplicationFiled: January 3, 2018Publication date: May 24, 2018Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
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Patent number: 9887204Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: GrantFiled: May 2, 2017Date of Patent: February 6, 2018Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan
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Patent number: 9824965Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.Type: GrantFiled: January 5, 2017Date of Patent: November 21, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Qian Tao, Boon Keat Tan, Richard Lum Kok Keong
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Publication number: 20170309818Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: ApplicationFiled: July 6, 2017Publication date: October 26, 2017Inventors: Tsz W. Chan, D.V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
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Patent number: 9793203Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The isolation device comprises a first plate that is electrically coupled to the first circuit, and a second plate that is electrically coupled to the second circuit. The first plate is configured to transmit the first signal from to a second plate that is electrically isolated from the first plate. The first plate and the second plate is surrounded by an isolation material. The isolation device further comprises at least one trench that extend at least partially through the isolation material in a direction that is substantially perpendicular to the first plate and the second plate. The at least one trench may circumscribe one of the first plate and the second plate.Type: GrantFiled: October 2, 2015Date of Patent: October 17, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Qian Tao, Richard Lum Kok Keong, Boon Keat Tan
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Publication number: 20170236828Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan
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Patent number: 9716225Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: GrantFiled: September 3, 2014Date of Patent: July 25, 2017Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
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Patent number: 9698343Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: November 9, 2015Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D.V. Nirmal Ramaswamy
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Publication number: 20170186757Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: March 15, 2017Publication date: June 29, 2017Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D.V. Nirmal Ramaswamy
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Patent number: 9673203Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: GrantFiled: March 9, 2016Date of Patent: June 6, 2017Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan
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Publication number: 20170117217Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Qian Tao, Boon Keat Tan, Richard Lum Kok Keong
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Publication number: 20170098603Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The isolation device comprises a first plate that is electrically coupled to the first circuit, and a second plate that is electrically coupled to the second circuit. The first plate is configured to transmit the first signal from to a second plate that is electrically isolated from the first plate. The first plate and the second plate is surrounded by an isolation material. The isolation device further comprises at least one trench that extend at least partially through the isolation material in a direction that is substantially perpendicular to the first plate and the second plate. The at least one trench may circumscribe one of the first plate and the second plate.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: Qian Tao, Richard Lum Kok Keong, Boon Keat Tan