Patents by Inventor Qiang DOU

Qiang DOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078413
    Abstract: Disclosed is a massive data-driven method for automatically locating a mine microseismic source, including: constructing a microseismic wave calibration data set by using a large-scale seismic data set containing seismic signals and non-seismic signals; constructing a pre-training calibration model based on a full convolution neural network through deep learning of a seismic wave calibration data set; using microseismic data of mine sites for transfer learning of an initial arrival time calibration model to construct an arrival time automatic calibration model suitable for mine microseismic signals; and automatically as well as accurately locating mine microseismic events based on an isokinetic homogeneous isotropic velocity model by using an optimization algorithm to deduce arrival time errors and through repeated iteration and fine-tuning.
    Type: Application
    Filed: December 9, 2022
    Publication date: March 7, 2024
    Inventors: Anye CAO, Changbin WANG, Xu YANG, Yaoqi LIU, Sen LI, Qiang NIU, Linming DOU
  • Patent number: 11923532
    Abstract: A pre-lithiated silicon-based anode includes a silicon-based anode, lithium disposed on a surface or in an interior of the silicon-based anode, and a protective coating on the surface of the silicon-based anode. The pre-lithiated silicon-based anode allows subsequent processing to be performed safely in the atmosphere.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 5, 2024
    Assignee: Robert Bosch GmbH
    Inventors: Rongrong Jiang, Jingjun Zhang, Yuqian Dou, Lei Wang, Chuanling Li, Yunhua Chen, Xiaogang Hao, Qiang Lu
  • Publication number: 20230069047
    Abstract: A microprocessor comprising a cryptographic engine and a controller. The controller is connected to the cryptographic engine and configured to receive a plurality of access requests from a plurality of execution environments, respectively and respond to one of the plurality of access requests and instruct the cryptographic engine to execute a cryptographic algorithm.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 2, 2023
    Inventors: Yanzhao FENG, Qiang DOU, Yufeng GUO, Ming ZHANG, Zhuo MA, Qiaoqiao HU, Yongpeng LIU
  • Publication number: 20230068658
    Abstract: A microprocessor includes a cryptographic engine and a controller. The cryptographic engine is configured to execute a cryptographic algorithm. The controller is connected to the cryptographic engine. The controller is configured to receive an access request from a first execution environment. The access request accesses the cryptographic engine to execute the cryptographic algorithm. The access request includes at least identification information. The identification information indicates that the access request is from the first execution environment. The first execution environment is an execution environment of a number N execution environments. N is an integer greater than or equal to 1. The controller is further configured to, based on the identification information, instruct the cryptographic engine to execute the cryptographic algorithm that needs to be executed required by the access request.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 2, 2023
    Inventors: Qiang DOU, Yanzhao FENG, Yufeng GUO, Ming ZHANG, Zhuo MA, Qingshan ZHU, Zhiqiang CHEN
  • Publication number: 20230069781
    Abstract: A microprocessor includes a cryptographic engine, M buffer units, and a controller. The cryptographic engine is configured to execute cryptographic algorithms. The M buffer units are configured to cache data required by an access request of a corresponding execution environment. M is an integer greater than or equal to 1. The controller is connected to the cryptographic engine and the M buffer units. The controller is configured to receive the access request from a first execution environment and instruct the cryptographic engine to execute the cryptographic algorithm requested by the access request using the required data cached by the buffer unit corresponding to the first execution environment from which the access request comes. The access request is used to access the cryptographic engine to execute a cryptographic algorithm. The first execution environment is one execution environment among N execution environments. N is an integer greater than or equal to 1.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 2, 2023
    Inventors: Yufeng GUO, Qiang DOU, Yanzhao FENG, Zhuo MA, Ming ZHANG, Qingshan ZHU, Jianyue WANG, Qiang DENG
  • Patent number: 11334668
    Abstract: A method and a device for securing a cache against side channel attacks are provided. An allocator identifier ALLOCATOR field is added to each cache entry in the present disclosure. Whenever an entry is allocated in the cache, the identifier of the software domain currently running on the processor is filled into the ALLOCATOR field of the allocation entry. When accessing the cache, the cache entry can be hit only if the identifier of the software domain currently running on the processor is identical to the ALLOCATOR field in the cache entry. If the cache entry to be replaced is invalid or its ALLOCATOR field is identical to the identifier of the software domain currently running on the processor, then the existing entry in the cache is replaced directly; otherwise, the entire cache is emptied.
    Type: Grant
    Filed: December 30, 2018
    Date of Patent: May 17, 2022
    Assignee: PHYTIUM TECHNOLOGY CO., LTD.
    Inventors: Qiang Dou, Tianlei Zhao, Chengyi Zhang, Jun Gao, Hongbo Xue, Xiaoyan Liu, Wenzhe Li, Yujiao Wang, Jiahong Yuan, Longpeng Sun, Shuijingtao Li, Zhe Ding, Xiaofeng Wang, Xiaodao Wang, Wenhui Cao, Shuaike Zheng, Boqing You, Yuan Yuan, Xiaoli Zou
  • Publication number: 20200242243
    Abstract: A method and a device for securing a cache against side channel attacks are provided. An allocator identifier ALLOCATOR field is added to each cache entry in the present disclosure. Whenever an entry is allocated in the cache, the identifier of the software domain currently running on the processor is filled into the ALLOCATOR field of the allocation entry. When accessing the cache, the cache entry can be hit only if the identifier of the software domain currently running on the processor is identical to the ALLOCATOR field in the cache entry. If the cache entry to be replaced is invalid or its ALLOCATOR field is identical to the identifier of the software domain currently running on the processor, then the existing entry in the cache is replaced directly; otherwise, the entire cache is emptied.
    Type: Application
    Filed: December 30, 2018
    Publication date: July 30, 2020
    Applicant: PHYTIUM TECHNOLOGY CO.,LTD.
    Inventors: Qiang DOU, Tianlei ZHAO, Chengyi ZHANG, Jun GAO, Hongbo XUE, Xiaoyan LIU, Wenzhe LI, Yujiao WANG, Jiahong YUAN, Longpeng SUN, Shuijingtao LI, Zhe DING, Xiaofeng WANG, Xiaodao WANG, Wenhui CAO, Shuaike ZHENG, Boqing YOU, Yuan YUAN, Xiaoli ZOU