Abstract: The present invention provides a hardware-aware mixed-precision quantization method and system based on a greedy search. It comprises quantizing all layers in the neural network to the uniform bit-width, conducting training-aware quantization, and acquiring the trained model, baseline inference accuracy, and total bit operation counts. Each layer in the neural network undergoes post-training quantization with low precision individually, and the corresponding inference accuracy and total bit operation counts for each layer are recorded. Single-layer sensitivity is computed based on the baseline inference accuracy, total bit operation counts, and the inference accuracy and total bit operation counts of each layer and guides the current total bit operation counts until reaching the preset maximum bit operation counts. Meanwhile, quantized layers and precision are recorded, determining the mixed-precision quantization strategy.

Abstract: A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.

Abstract: A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.