Patents by Inventor Qiang Fang

Qiang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768058
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Qiang Fang, Christian Witt
  • Patent number: 9741610
    Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qiang Fang, Zhiguo Sun, Jiehui Shu
  • Patent number: 9711447
    Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Qiang Fang, Daniel W. Fisher, Haigou Huang, Jinping Liu, Haifeng Sheng, Zhiguo Sun
  • Publication number: 20170093310
    Abstract: A motor controller, including: a Bluetooth communication unit and a motor control unit. The Bluetooth communication unit includes: a power supply part, a Bluetooth module, and an interface circuit. The motor control unit includes an input port of a rotational speed adjusting signal. The power supply part supplies power to the Bluetooth module and the interface circuit. The Bluetooth module enables the motor control unit to communicate with an external device. The Bluetooth module inputs a PWM signal into the input port of the rotational speed adjusting signal of the motor control unit via the interface circuit.
    Type: Application
    Filed: April 26, 2016
    Publication date: March 30, 2017
    Inventors: Qiang FANG, Wenqing BIAN, Songfa TANG, Qingmei JIAO, Lijuan LI
  • Patent number: 9595493
    Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhiguo Sun, Qiang Fang, Huang Liu, Haigou Huang, Jiehui Shu, Jin Ping Liu
  • Publication number: 20170047242
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 16, 2017
    Inventors: Zhiguo Sun, Qiang Fang, Christian Witt
  • Publication number: 20170047282
    Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 16, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Zhiguo SUN, Qiang FANG, Huang LIU, Haigou HUANG, Jiehui SHU, Jin Ping LIU
  • Publication number: 20160373386
    Abstract: Embodiments of the present invention provide a display style adjustment method and system, and a device. The display style adjustment system in the present invention is applicable to instant messaging and includes: an obtaining module, configured to obtain a relationship between at least two terminals in an instant messaging group; a determining module, configured to determine, based on the relationship between the at least two terminals obtained by the obtaining module, to recommend a target display style to some or all terminals of the at least two terminals; and a selection module, configured to select the target display style according to an indication of the determining module and a preset rule of the system, so that an instant message is displayed in the target display style on the some or all terminals.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Junxiu Wang, Qiang Fang
  • Publication number: 20160365277
    Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Qiang FANG, Zhiguo SUN, Jiehui SHU
  • Patent number: 9518151
    Abstract: The present invention belongs to the field of preparation of high performance polymers, and specifically relates to a low dielectric constant polymer containing dinaphthyl and hexafluorocyclobutyl ether units, and preparation method and use thereof. The polymer is prepared as follows: under the effect of an alkali, 1-naphthol bromotetrafluoroethane ether is prepared from 1-naphthol and tetrafluorodibromoethane in an organic solvent, and then reduced by a zinc powder so as to obtain 1-naphthol trifluorovinyl ether. 1-naphthol trifluorovinyl ether is treated at a high temperature to obtain a bisnaphthol hexafluorocyclobutyl ether monomer. The monomer is subjected to oxidative coupling in the presence of ferric trichloride so as to obtain a thermal polymer containing dinaphthyl and hexafluorocyclobutyl structural units with a good film-forming property, and in a nitrogen atmosphere, the temperature for 5% weight loss (Td5%) of the obtained film is 437° C., and the carbon residue yield at 1000° C. is 54.24%.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 13, 2016
    Assignee: Shanghai Institute of Organic Chemistry, Chinese Academy of Sciences
    Inventors: Qiang Fang, Chao Yuan, Kaikai Jin, Yingchun Liu, Shen Diao, Kai Li
  • Patent number: 9466723
    Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Haigou Huang, Qiang Fang, Jin Ping Liu, Huang Liu
  • Publication number: 20160156117
    Abstract: A card edge connector for connecting an electrical card to a PCB (printed circuit board), includes a terminal block with an elongate inserting slot for the electrical card to insert into and at least a locking device separate from the terminal block. The locking device includes at least one supporting portion and at least one locking portion. The supporting portion defines a blind hole by downwardly recessing an upper surface thereof for mating with the locking portion, and includes a mounting portion opposite to the blind hole along a vertical direction for retaining the supporting portion to the PCB. The electrical card is positioned and retained between the locking portion and the supporting portion. The locking device would make good use of a space of the PCB.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 2, 2016
    Inventors: ZHEN-HUA WANG, QIANG FANG
  • Publication number: 20160060394
    Abstract: The present invention belongs to the field of preparation of high performance polymers, and specifically relates to a low dielectric constant polymer containing dinaphthyl and hexafluorocyclobutyl ether units, and preparation method and use thereof. The polymer is prepared as follows: under the effect of an alkali, 1-naphthol bromotetrafluoroethane ether is prepared from 1-naphthol and tetrafluorodibromoethane in an organic solvent, and then reduced by a zinc powder so as to obtain 1-naphthol trifluorovinyl ether. 1-naphthol trifluorovinyl ether is treated at a high temperature to obtain a bisnaphthol hexafluorocyclobutyl ether monomer. The monomer is subjected to oxidative coupling in the presence of ferric trichloride so as to obtain a thermal polymer containing dinaphthyl and hexafluorocyclobutyl structural units with a good film-forming property, and in a nitrogen atmosphere, the temperature for 5% weight loss (Td5%) of the obtained film is 437° C., and the carbon residue yield at 1000° C. is 54.24%.
    Type: Application
    Filed: November 20, 2013
    Publication date: March 3, 2016
    Inventors: Qiang FANG, Chao YUAN, Kaikai JIN, Yinchun LIU, Shen DIAO, Kai LI
  • Patent number: 8170055
    Abstract: In one embodiment of a method of translating a RADIUS message to a Diameter message, an access request message in RADIUS is translated to a credit control request message in Diameter. In one embodiment of a method of translating a Diameter message to a RADIUS message, a credit control answer message is translated to an access accept message.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: May 1, 2012
    Assignee: Alcatel Lucent
    Inventors: Qiang Fang, Min Liu, Yile Enoch Wang, Ying Wang, Rui Yun Wu, Da Bin Yuan