Abstract: A method and a system for simulating contact and interaction between a support member and a chamber surrounding rock mass are provided in the application.

Abstract: A system controller determines a to-be-collected first logical chunk group. The first logical chunk group includes a first data logical chunk located in a first solid state disk of the plurality of solid state disks. Valid data is stored in a first logical address in the first logical chunk group, and there is a correspondence between the first logical address and an actual address in which the valid data is stored. The system controller creates a second logical chunk group. At least one second data logical chunk in the second logical chunk group is distributed in the solid state disk in which the first data logical chunk storing a valid data is located in order to ensure that the valid data is migrated from the first logical chunk group to the second logical chunk group, but an actual address of the valid data remains unchanged.

Abstract: Disclosed in the present invention are a pyridinyl morpholine compound, a preparation method therefor, and an application thereof. The present invention provides a pyridinyl morpholine compound as represented by formula I, a pharmaceutically acceptable salt thereof or a hydrate of the pharmaceutically acceptable salt thereof. The compound can be used as an antagonist for one or more of D2, D3 or 5-HT2A, and is used for preparing a drug for treating schizophrenia.

Abstract: Disclosed are a benzonitric heterocyclic compound, a preparation method therefor and the use thereof. Provided in the present invention is a benzonitric heterocyclic compound represented by formula I, or a pharmaceutically acceptable salt thereof, which can be used as a histone deacetylase inhibitor, has a selective inhibitory effect on HDAC6, and has characteristics such as a high efficiency, low toxicity and ideal pharmacokinetic properties.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.