Patents by Inventor Qiang Shu

Qiang Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240148354
    Abstract: A stethoscope kit includes a storage cylinder, a protective shell and an electronic stethoscope. The storage cylinder includes a base and a cylinder body. The protective shell is configured to be sleeved on the cylinder body. Two sides of the cylinder body are each symmetrically provided with a groove. A bottom of the groove is provided with an accommodating groove configured to accommodate the electronic stethoscope. A bottom of the accommodating groove is attached to a bottom of the electronic stethoscope through an attraction mechanism. A charging device is provided in the cylinder body. When the electronic stethoscope is placed in the accommodating groove, the charging device is configured to charge the electronic stethoscope.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 9, 2024
    Inventors: Weize XU, Qiang SHU
  • Publication number: 20220351965
    Abstract: A mask pattern for forming the semiconductor structure is provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventors: Qiang SHU, Yingchun ZHANG, Liusha QIN
  • Patent number: 11424122
    Abstract: A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 23, 2022
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiang Shu, Yingchun Zhang, Liusha Qin
  • Publication number: 20210210343
    Abstract: A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.
    Type: Application
    Filed: September 29, 2020
    Publication date: July 8, 2021
    Inventors: Qiang SHU, Yingchun ZHANG, Liusha QIN
  • Patent number: 9869914
    Abstract: The present disclosure discloses an array substrate and a display device so as to alleviate the toothed edge appearance when an image is displayed in a dual-gate array substrate structure. The array substrate includes at least one row of pixel elements, a first gate line, and a second gate line. The first gate line and the second gate line are disposed on the same side of the least one row of pixel elements. Thin film transistors are disposed in the pixel elements, and gates of the thin film transistors in two adjacent pixel elements are coupled with the first gate line and the second gate line, respectively.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 16, 2018
    Assignees: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Wei Huang, Qiang Shu
  • Patent number: 9223229
    Abstract: An exposure method and an exposure device are provided. An exemplary exposure device includes a stage, a first clamp holder, a second clamp holder, an optical projection unit, a first alignment detection unit, and/or a second alignment detection unit. The stage includes a first region and a second region. The first clamp holder is located in the first region and adapted for holding a first substrate, and the second clamp holder is located in the second region and adapted for holding a second substrate. The optical projection unit is located above the stage and adapted for exposure of the first substrate or the second substrate. The first alignment detection unit is adapted for detecting alignment marks of the first substrate. The second alignment detection unit is adapted for detecting alignment marks of the second substrate. The exposure device can accurately position the stage and improve production yield.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 29, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP
    Inventors: Qiang Wu, Jing'an Hao, Chang Liu, Xin Yao, Tianhui Li, Qiang Shu, Yiming Gu
  • Publication number: 20150355517
    Abstract: The present disclosure discloses an array substrate and a display device so as to alleviate the toothed edge appearance when an image is displayed in a dual-gate array substrate structure. The array substrate includes at least one row of pixel elements, a first gate line, and a second gate line. The first gate line and the second gate line are disposed on the same side of the least one row of pixel elements. Thin film transistors are disposed in the pixel elements, and gates of the thin film transistors in two adjacent pixel elements are coupled with the first gate line and the second gate line, respectively.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 10, 2015
    Inventors: Wei HUANG, Qiang SHU
  • Patent number: 9134624
    Abstract: The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 15, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP
    Inventors: Qiang Wu, Jing'an Hao, Chang Liu, Xin Yao, Tianhui Li, Qiang Shu, Yiming Gu