Patents by Inventor Qiang Tang

Qiang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250126521
    Abstract: In an example, a method for provisioning a cell site in a 5G RAN may include receiving a plurality of steps involved in provisioning the cell site for the 5G RAN. In an example, provisioning the cell site may include provisioning of a physical infrastructure layer, a container orchestration platform on the physical infrastructure layer, and a containerized network function (CNF) instance associated with the 5G RAN in the container orchestration platform. Further, the method may include converting the plurality of steps into a dependency graph of tasks. The dependency graph may represent workflows and relationships between the tasks. Furthermore, based on feeding the dependency graph as an input to an orchestrator, the method may include provisioning the cell site by executing the tasks in an order according to the dependency graph.
    Type: Application
    Filed: January 5, 2024
    Publication date: April 17, 2025
    Inventors: ASHVIN LAKSHMIKANTA, QIANG TANG, KIRAN KUMAR CHERIVIRALA, ROHIT MUTTEPWAR, SIVA POLEPALLI, HEMANT SADANA, WEIQING WU, SURESHBABU KOYADAN CHATHOTH, PRAVEEN SAXENA, ANURAG DWIVEDI
  • Publication number: 20250126023
    Abstract: An example method for managing a cell site in a 5G RAN may include determining a physical infrastructure layer, a container orchestration platform on the physical infrastructure layer, and a CNF instance associated with the 5G RAN in the container orchestration platform based on a site identifier associated with the cell site. Based on the physical infrastructure layer, the container orchestration platform, and the CNF instance, the method may include building a logical site resource map representing topological information of the cell site. Further, the method may include monitoring and/or managing the cell site using the logical site resource map.
    Type: Application
    Filed: January 5, 2024
    Publication date: April 17, 2025
    Inventors: QIANG TANG, ASHVIN LAKSHMIKANTA, KIRAN KUMAR CHERIVIRALA, ROHIT MUTTEPWAR, SIVA POLEPALLI, HEMANT SADANA, PRAVEEN SAXENA, WEIQING WU, SURESHBABU KOYADAN CHATHOTH, ANURAG DWIVEDI
  • Publication number: 20250089521
    Abstract: A display panel is provided, including a flat display region, and a fixed region and a sliding-scrolling region on two sides of the flat display region in a first direction, the fixed region is adhered with a middle frame, the flat display region is configured to display images, the sliding-scrolling region is configured to form a rolled-up state and an extended state by sliding-scrolling, the sliding-scrolling region displays the image together with the flat display region in the extended state, on a plane perpendicular to the display panel, the display panel at least includes a display substrate, an adhesive layer disposed on the display substrate, and a cover plate layer on a side of the adhesive layer away from the display substrate, the cover plate layer at least includes a glass layer, the glass layer of at least one of the fixed region and the sliding-scrolling region has a structural hole.
    Type: Application
    Filed: June 30, 2022
    Publication date: March 13, 2025
    Inventors: Yongxiao GAO, Tiejun BI, Qiang TANG, Shiyou WANG, Danping SHEN, Wei ZENG, Zheng FANG, Yuqiang HUANG, Ziyan ZHONG
  • Patent number: 12229028
    Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and M redundant banks, where each of P, N and M is a positive integer, and N is greater than M. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. One of the M redundant banks is coupled with at least two main banks of the N main banks through the I/O circuit. The I/O control logic is configured to in responding to K main banks of the P groups of banks failed, determine the P×N working banks including K redundant banks of P×M redundant banks, where K is a positive integer not greater than P, and control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: February 18, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Qiang Tang
  • Patent number: 12231398
    Abstract: Some embodiments of the invention provide a method of sending data in a network that includes multiple worker nodes, each worker node executing at least one set of containers, a gateway interface, and a virtual local area network (VLAN) tunnel interface. The method configures the gateway interface of each worker node to associate the gateway interface with multiple subnets. Each subnet is associated with a namespace, a first worker node executes a first set of containers of a first namespace, and a second worker node executes a second set of containers of the first namespace and a third set of containers of a second namespace. The method sends data between the first set of containers and the second set of containers through a VLAN tunnel between the first and second worker nodes.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 18, 2025
    Assignee: VMware LLC
    Inventors: Qiang Tang, Zhaoqian Xiao
  • Patent number: 12230897
    Abstract: A circuit board assembly includes a connection circuit board, a near field communication antenna and solders. The connection circuit board includes circuit board pads. The near field communication antenna is attached to the connection circuit board, and the near field communication antenna includes: an antenna coil, antenna pads electrically connected to the antenna coil, and through holes penetrating the antenna pads and disposed opposite to the circuit board pads. The solders are connected to the circuit board pads through the through holes.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 18, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fengxian Wang, Chuanyan Lan, Qiang Tang, Xianlei Bi
  • Patent number: 12228970
    Abstract: Provided is a flexible display structure, including a reinforcing strip, and a flexible display panel and a supporting layer that are laminated. The flexible display panel is provided with a first surface and a second surface opposite to each other, and a first side surface connecting the first surface and the second surface, and the reinforcing strip is disposed on the first side surface and configured to adhere the flexible display panel to the supporting layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: February 18, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shaokui Liu, Wei Qing, Qiang Tang, Zhihui Wang, Xingguo Liu, Xianlei Bi
  • Patent number: 12219743
    Abstract: A display module and an electronic device are provided. The display module includes a display film layer, a heat dissipation film layer, a support plate and an elastic thermal conductive sheet. The display film layer and the heat dissipation film layer include a flat area and bending areas, and an angle exists between a tangent of a curved surface formed by the bending areas and a plane where the flat area is located. The display film layer is stacked on a first surface of the heat dissipation film layer. The support plate is connected to a position where the flat area of a second surface of the heat dissipation film layer is located, and the elastic thermal conductive sheet is connected to a position where the bending areas of the second surface of the heat dissipation film layer are located. The first surface and the second surface are opposite surfaces.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 4, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xin Qing, Li Zeng, Qiang Tang, Linhuan Yan, Liang Chen, Jinglei Wang
  • Patent number: 12211537
    Abstract: A method of programming a ferroelectric memory device is disclosed. The method includes applying a first voltage to a first word line; applying a second voltage to the first word line; and applying a pass voltage to a second word line during a period of applying the first voltage to the first word line and during a period of applying the second voltage to the first word line. The pass voltage is between the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: January 28, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Qiang Tang
  • Publication number: 20240431056
    Abstract: Provided are a flexible display structure. The flexible display structure includes a reinforcing strip, and a flexible display panel and a transparent cover plate that are laminated, wherein the transparent cover plate is provided with a fifth surface and a sixth surface opposite to each other, and a third side surface connecting the fifth surface to the sixth surface; and the flexible display panel is adhered to the transparent cover plate via an optical adhesive layer, and the reinforcing strip is disposed at least on the third side surface.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Inventors: Shaokui LIU, Wei QING, Qiang TANG, Zhihui WANG, Xingguo LIU, Xianlei BI
  • Publication number: 20240431111
    Abstract: A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.
    Type: Application
    Filed: September 9, 2024
    Publication date: December 26, 2024
    Inventors: Jason GUO, Qiang TANG
  • Publication number: 20240412226
    Abstract: A system and method for evaluating performance of a model used in providing a response to a product help inquiry includes receiving the product help inquiry, classifying the product help inquiry as being associated with a topic related to a product, and retrieving a path of actions provided in a help documentation associated with the topic. A prompt is also generated based on the product help inquiry for transmission to the model and a response is provided by the model, before a path of actions included the response is extracted. Contextual embeddings for the extracted path are generated and semantic similarities between contextual embeddings for the extracted path and embeddings generated for an expected response are measured. By generating contextual embeddings for the extracted path instead of the entire response, resources required for evaluating the response are significantly reduced. A path coverage metric is measured for the extracted path.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Kartik MATHUR, Andrew David MYERS, Yinyu Jin QUAN, Dalia Ahmed Essa SWELLUM, Fa Qiang TANG, Justin Jack TRAENKENSCHUH
  • Patent number: 12161034
    Abstract: The present disclosure provides a display apparatus, a display panel of which includes a panel chip; a second bonding region of a main circuit board is provided with second display terminals coupled with first display terminals and second touch control terminals coupled with first touch control terminals; each of segment touch control lines includes a first segment coupled between one second touch control terminal and one main connector in a first region, and a second segment coupled between a touch control chip and one main connector in a second region; a third region and a fourth region of a jumper connection circuit board are bonded with the first region and the second region respectively; the segment touch control lines are in one-to-one correspondence with jumper connection lines, each jumper connection line is coupled between one jumper connector in the third region and one jumper connector in the fourth region.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: December 3, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanzhang Zhu, Ren Xiong, Qiang Tang, Guoqiang Wu, Fei Shang, Haijun Qiu
  • Publication number: 20240395176
    Abstract: Provided are a supporting backplane and a display apparatus. The supporting backplane is arranged at one side of a flexible display panel, and the supporting backplane at least comprises a main bending area, wherein a bending axis corresponding to the main bending area extends in a first direction; the main bending area is provided with a plurality of first hollow holes, the plurality of first hollow holes being arranged in an array in the first direction and a second direction, which is orthogonal to the first direction; each of the first hollow holes is provided with a first middle hole area, and first arc-shaped hole areas located at two sides of the first middle hole area in the first direction.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zuquan CHEN, Wei QING, Xingguo LIU, Shaokui LIU, Zhihui WANG, Wei ZENG, Danping SHEN, Qiang TANG, Ce WANG
  • Patent number: 12142327
    Abstract: A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 12, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qiang Tang, Xiang Fu
  • Publication number: 20240360030
    Abstract: The present disclosure provides a method for manufacturing an ultra-thin glass substrate, including: providing a large glass sheet including a plurality of to-be-cut glass substrates, each to-be-cut glass substrate including a bendable region and a non-bendable region arranged at two sides of the bendable region along a first direction; cutting each to-be-cut glass substrate along an edge of the bendable region to form two slits arranged opposite to each other; performing a double-sided thinning operation on the large glass sheet, and performing an edge etching operation on the edge of the bendable region; cutting each to-be-cut glass substrate along an edge of the non-bendable region through a laser to obtain a glass substrate; performing a chemical tempering operation on the glass substrate; and performing micro-etching treatment on a surface of the chemically-tempered glass substrate. The present disclosure further provides the ultra-thin glass substrate and a display device.
    Type: Application
    Filed: May 31, 2022
    Publication date: October 31, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongxiao Gao, Tiejun Bi, Shiyou Wang, Qiang Tang, Xiaolin Xu, Zheng Fang
  • Patent number: 12133385
    Abstract: A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: October 29, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jason Guo, Qiang Tang
  • Publication number: 20240349575
    Abstract: Provided are a cover plate, a display module, and a display device. The cover plate includes: a cover plate base (10) and an anti-fingerprint film layer (11) disposed on a side of the cover plate base (10); and an electrostatic transfer layer (20) disposed between the cover plate base (10) and the anti-fingerprint film layer (11) or disposed on a side of the cover plate base (10) facing away from the anti-fingerprint film layer (11).
    Type: Application
    Filed: July 31, 2023
    Publication date: October 17, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xi Zhu, Chen Li, Qiang Tang, Xu Fan, Lei Zhang
  • Patent number: 12119084
    Abstract: A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: October 15, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Tang, Chunyuan Hou
  • Patent number: D1045430
    Type: Grant
    Filed: May 28, 2024
    Date of Patent: October 8, 2024
    Inventor: Qiang Tang