Abstract: Systems, devices, and methods for fabricating filling structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes: a semiconductor structure including a stack of conductive layers and isolating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes contact structures extending through at least a part of the connection region along the first direction. A conductive layer of the stack is coupled to a contact structure through a connection layer in the connection region. The conductive layer is in contact with the connection layer along the second direction. A filling film is in a space between a portion of the conductive layer and at least one isolating layer adjacent to the conductive layer.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: A three-dimensional (3D) memory device includes a staircase, a plurality of contacts, a plurality of groups of support structures, and a fourth support structure between adjacent groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction. Each of the groups of support structures includes three support structures. Projections of the three support structures form a triangular shape in a plane parallel to the first direction. The plurality of contacts each is surrounded by a respective group. A projection of one of the contacts overlaps with the triangular shape of the respective group.

Abstract: A semiconductor device and a manufacturing method thereof, a memory and a memory system are disclosed. The method includes: providing a substrate and stacked layers on the substrate, the stacked layers comprising interlayer sacrificial layers and interlayer insulating layers which are alternately stacked; removing part of the interlayer sacrificial layer to form a gate gap; sequentially forming a protection layer and a gate structure in the gate gap; forming a contact hole extending from a side of the stacked layers facing away from the substrate into a remaining interlayer sacrificial layer and exposing the protection layer; removing the protection layer exposed in the contact hole to expose the gate structure; forming a contact structure in the contact hole in such a way that the contact structure is connected with the gate structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure including alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions, and bridge structures connecting the two core regions and extending through the staircase region in a first direction. A first bridge structure of the bridge structures includes at least two current paths between the two core regions.

Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a substrate, a stack structure laterally formed on the substrate and having a central area and a staircase area, a plurality of channel structures extending vertically in the central area, a plurality of dummy channel structures extending vertically in the staircase area, and a plurality of contact plugs formed in the staircase area and being electrically connected to the stack structure. A vertical projection of at least one of the dummy channel structures on a lateral surface of the substrate includes a two-dimensional shape with directionality.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a gate stack structure including a core area and a step area which are disposed in juxtaposition and in direct contact in a first direction; a dummy separation structure penetrating through the step area in the first direction; and a gate separation structure penetrating through the core area in the first direction, the gate separation structure having a first end in contact with the dummy separation structure in the first direction, the dummy separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end.

Abstract: A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are alternatingly arranged in a vertical direction perpendicular to a substrate of the semiconductor device. The stack includes a first array region and an adjacent first staircase region. The semiconductor device includes a dummy channel structure that extends in the vertical direction through the word line layers and the insulating layers in the first staircase region of the stack. At least one of the word line layers is located further away from a central axis of the dummy channel structure than the insulating layers adjacent to the at least one of the word line layers.