Patents by Inventor Qiankun YANG

Qiankun YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ternary T arithmetic circuit
    Patent number: 8937493
    Abstract: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: January 20, 2015
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Xuesong Zheng, Qiankun Yang
  • TERNARY T ARITHMETIC CIRCUIT
    Publication number: 20140292373
    Abstract: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS.
    Type: Application
    Filed: March 20, 2014
    Publication date: October 2, 2014
    Applicant: NINGBO UNIVERSITY
    Inventors: Pengjun WANG, Xuesong ZHENG, Qiankun YANG